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IEEE Design & Test of Computers

Issue 3 • Date June 1988

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Displaying Results 1 - 5 of 5
  • Design verification of the WE 32106 math accelerator unit

    Publication Year: 1988, Page(s):11 - 21
    Cited by:  Papers (9)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (961 KB)

    An overview is given of the MAU, an IEEE-compatible floating-point accelerator that operates as a coprocessor for the WE 32100 CPU. The chip provides virtually all the features that the IEEE-754 floating-point standard requires, with added software that provides a fully conforming system. A description is then given of the approach used for its design verification, which resulted in a unit that ha... View full abstract»

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  • Behavioral model synthesis with Cones

    Publication Year: 1988, Page(s):22 - 30
    Cited by:  Papers (17)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (669 KB)

    The Cones synthesis system for automatic generation of VLSI implementations is discussed. Named for the cones in sequential logic, Cones takes behavioral models written in C and produces gate-level implementations in technologies such as standard cells and programmable logic arrays or programmable logic devices. The overall design is produced faster, more efficiently, and with fewer errors. Design... View full abstract»

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  • Behavioral-level fault simulation

    Publication Year: 1988, Page(s):31 - 42
    Cited by:  Papers (20)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1070 KB)

    An approach to fault simulation is presented in which behavioral fault models represent complex failures in VLSI designs. Errors are deliberately introduced into the description of a design that contains no faults. These errors can be fault values of variables that represent state or timing parameters, a faulty description that is substituted for part of the good description, or a combination of t... View full abstract»

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  • Algorithms for automatic test-pattern generation

    Publication Year: 1988, Page(s):43 - 55
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1051 KB)

    Three well-known algorithms for the automatic test pattern generation (ATPG) for digital circuits are the D algorithm, Podem, and Fan. The author introduces the concept of test generation and analyzes the way each algorithm uses search and backtracking techniques to sensitize a fault and propagate it to an observable point. The heuristics used to guide ATPG search and the notation used to represen... View full abstract»

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  • Throughput advantages of asynchronous prober control

    Publication Year: 1988, Page(s):56 - 63
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (486 KB)

    Parallel testing of memories at the wafer-sort stage can offer significant throughput advantages. Accepted methods at this state involve synchronous prober control. A model is presented that shows how asynchronous prober control can increase throughput 36% over that possible with synchronous control.<> View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Krishnendu Chakrabarty