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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 5 • Date May 2007

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Displaying Results 1 - 25 of 31
  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): C2
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  • Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

    Page(s): 933 - 940
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    Design procedures for three-stage CMOS operational transconductance amplifiers employing nested-Miller frequency compensation are presented in this paper. After describing the basic methodology on a Class-A topology, some modifications, to increase swing, slew-rate and current drive capability, are subsequently discussed for a Class-AB solution. The approaches developed are simple as they do not introduce unnecessary circuit constraints and yield accurate results. They are hence suited for a pencil-and-paper design, but can be easily integrated into an analog knowledge-based computer-aided design tool. Experimental prototypes, designed in a 0.35-mum technology by following the proposed procedures, were fabricated and tested. Measurement results were found in close agreement with the target specifications View full abstract»

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  • An Analog Approach to Suppressing In-Band Narrow-Band Interference in UWB Receivers

    Page(s): 941 - 950
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    Due to the huge bandwidth of ultra-wide-band (UWB) systems, in-band narrow-band interference (NBI) may hinder receiver performance. Sources of potential NBI that lie within the IEEE 802.15.3a UWB bandwidth are presented. To combat interference in multi-band orthogonal frequency-division multiplexing (MB-OFDM) UWB systems, an analog notch filter is designed to be included in the UWB receive chain. The filter's architecture is based on feedforward subtraction of the interference, and includes a least-mean-square (LMS) tuning scheme to match amplitudes of the two paths. An 8-bit discrete control is used to adjust the filter's center frequency across the UWB baseband. It was fabricated in TSMC's 0.18-mum process, and experimental results are provided View full abstract»

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  • Indirect Programming of Floating-Gate Transistors

    Page(s): 951 - 963
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    Floating-gate (FG) transistors are useful for precisely programming a large array of current sources. Present FG programming techniques require disconnection of the transistor from the rest of its circuit while it is being programmed. We present a new method of programming FG transistors that does not require this disconnection. In this indirect programming method, two transistors share a FG allowing one to exist directly in a circuit while the other is reserved for programming. Since the transistor does not need to be disconnected from the circuit to program it, the switch count is reduced, resulting in fewer parasitics and better overall performance. Additionally, the use of these indirectly programmed FG transistors allows a circuit to be tuned such that the effects of device mismatch are negated. Finally, the concept of run-time programming is introduced which allows a circuit to be recalibrated while it is still operating within its system View full abstract»

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  • Robust High-Gain Amplifier Design Using Dynamical Systems and Bifurcation Theory With Digital Postprocessing Techniques

    Page(s): 964 - 973
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    A CMOS differential positive feedback amplifier (PFA) and its inherent nonlinearity were analyzed. Based on nonlinear dynamical systems and bifurcation theory, we predicted bifurcation and hysteresis phenomena in the PFA. An algorithm, which can be implemented using simple digital logic, was developed to measure the PFA's open-loop stability as the bifurcation parameter changes. Parameter-tuning algorithms were constructed that systematically move the amplifier's operational point towards the bifurcation point, at which an infinite dc gain is achieved. In order to compensate for the PFA's high sensitivity to process and temperature variations, flexible analog design integrating digital programmability and adaptive digital postprocessing techniques were developed. This flexibility and postprocessing capability could dramatically enhance the PFA's yield. Full corner simulation results over wide temperature range verified the bifurcation phenomena and the effectiveness of the control algorithms. It is shown that this amplifier can maintain high performance in advanced digital CMOS technology at very low voltage supply. It is also demonstrated that the proposed approach offers a robust PFA design with both high yield and high performance View full abstract»

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  • Spectral Shaping of Dithered Quantization Errors in Sigma–Delta Modulators

    Page(s): 974 - 980
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    A well-known problem in sigma-delta (SigmaDelta) modulators is limit cycle oscillations, which can cause unwanted tones of significant power to appear in the quantization error. This problem becomes more severe as the amplitude of an input signal is small. The unwanted tones can be eliminated from the quantization error by employing a properly chosen random sequence to break up the limit cycle oscillations. However, the injected random sequence inevitably raises the noise floor in the signal band of interest, and thus degrades the signal-to-quantization-noise ratio (SQNR). This paper first presents a spectrally shaped noise generator and the theoretical basis for the behavior of the proposed generator is explained. Then we introduce a class of pseudorandom noise sequences with least significant bit dithering. The effectiveness of this class of dither sequences is demonstrated through a SigmaDelta modulator. Simulation results show that the proposed dither sequences improve the SQNR by more than 10 dB compared to the case wherein a white pseudorandom binary sequence is applied. Meanwhile, it is shown that the proposed sequences successfully break up the limit cycle oscillations for small input signals View full abstract»

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  • A Multichip Pulse-Based Neuromorphic Infrastructure and Its Application to a Model of Orientation Selectivity

    Page(s): 981 - 993
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    The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware implementations of massively parallel networks of integrate-and-fire neurons distributed over multiple chips. Address-event representation (AER) has long been considered a convenient transmission protocol for spike based neuromorphic devices. One missing, long-needed feature of AER-based systems is the ability to acquire data from complex neuromorphic systems and to stimulate them using suitable data. We have implemented a general-purpose solution in the form of a peripheral component interconnect (PCI) board (the PCI-AER board) supported by software. We describe the main characteristics of the PCI-AER board, and of the related supporting software. To show the functionality of the PCI-AER infrastructure we demonstrate a reconfigurable multichip neuromorphic system for feature selectivity which models orientation tuning properties of cortical neurons View full abstract»

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  • Generalized Comb Decimation Filters for Σ∆ A/D Converters: Analysis and Design

    Page(s): 994 - 1005
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    This paper addresses the design of generalized comb decimation filters, proposing some novel decimation schemes tailored to SigmaDelta modulators. We present a mathematical framework to optimize the proposed decimation filters in such a way as to increase the SigmaDelta quantization noise (QN) rejection around the so called folding bands, frequency intervals whose QN gets folded down to baseband because of the decimation process. Comparisons are given in terms of passband drop and selectivity with respect to classic comb filters with orders ranging from 3 to 6. As far as the practical implementation of the proposed filters is concerned, we present two different architectures, namely a recursive and a nonrecursive implementation, the latter of which constitutes the basis for realizing multiplier-less generalized comb filter (GCF) realizations. We propose a mathematical framework for evaluating the sensitivity of GCFs to the approximation of the multipliers embedded in the filter architectures. The considerations deduced from the sensitivity analysis, pave the way to an optimization algorithm useful for approximating the multipliers with power-of-2 coefficients View full abstract»

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  • Phase-Error Measurement and Compensation in PLL Frequency Synthesizers for FMCW Sensors—I: Context and Application

    Page(s): 1006 - 1017
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    The synthesis of linear frequency sweeps or chirps is required, among others, in frequency-modulated continuous-wave radar systems for object position estimation. Low phase and frequency errors in sweeps with high bandwidth are a prerequisite for good accuracy and resolution, but, in certain applications where high measurement rates are desired, the additional demand for short sweep cycles has to be met. Transient phenomena in dynamic synthesizers as well as nonlinear system behavior usually cause unknown phase errors in the system output. For the class of phase-locked-loop (PLL)-based frequency synthesizers, a novel output phase-measurement method and dedicated circuitry are proposed that allow significant reduction of phase errors by adaptive input predistortion. The measurement procedure is implemented within the PLL control circuitry and does not require external equipment. The application of this method to PLL system identification and linearization of extremely short frequency sweeps is shown View full abstract»

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  • Signature Testing of Analog and RF Circuits: Algorithms and Methodology

    Page(s): 1018 - 1031
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    There are mainly two factors responsible for rapidly escalating production test costs of today's RF and high-speed analog circuits: 1) the high cost of high-speed and RF automatic test equipments and 2) long test times required by elaborate performance tests. In this paper, we propose a low-cost signature test methodology for accelerated production testing of analog and RF integrated circuits. As opposed to prior work, the key contribution of this paper is a new test generation algorithm that directly tracks the ability of input test waveforms to predict the test specification values from the observed test response, even in the presence of measurement noise. The response of the device-under-test (DUT) is used as a "signature" from which all of the performance specifications are predicted. The applied test stimulus is optimized in such a way that the error between the measured DUT performances and the predicted DUT performances is minimized. While existing low-cost test approaches have only been applied to low- and medium-frequency analog circuits, the proposed methodology extends low-cost signature testing to RF integrated circuits by incorporating modulation of a baseband test stimulus and subsequent demodulation of the obtained response to obtain the DUT signature. The proposed low-cost solution can be easily built into a load board that can be interfaced to an inexpensive tester View full abstract»

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  • Characterization of a Flip-Flop Metastability Measurement Method

    Page(s): 1032 - 1040
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    We characterize a proposed metastability measurement system in which asynchronous data input and sampling clock frequencies trigger metastability. We develop an equation describing the time interval between data and clock inputs for practical frequencies and show that it takes on discrete values in the absence of jitter and that the presence of jitter perturbs these values. Finally, we present experimental results supporting our characterization View full abstract»

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  • A Residue-to-Binary Converter for a New Five-Moduli Set

    Page(s): 1041 - 1049
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    The efficiency of the residue number system (RNS) depends not only on the residue-to-binary converters but also the operand sizes and the modulus in each residue channel. Due to their special number theoretic properties, RNS with a moduli set consisting of moduli in the form of 2 nplusmn1 is more attractive than those with other forms of moduli. In this paper, a new five-moduli set RNS {2n-1,2n,2n+1,2n+1-1,2 n-1-1} for even n is proposed. The new moduli set has a dynamic range of (5n-1) bits. It incorporates two additional moduli to the celebrated three-moduli set, {2n-1,2n,2n +1} with VLSI efficient implementations for both the binary-to-residue conversion and the residue arithmetic units. This extension increases the parallelism and reduces the size of each residue channel for a given dynamic range. The proposed residue-to-binary converter relies on the properties of an efficient residue-to-binary conversion algorithm for {2n-1,2n,2n+1,2n+1-1} and the mixed-radix conversion (MRC) technique for the two-moduli set RNS. The hardware implementation of the proposed residue-to-binary converter employs adders as the primitive operators. Besides, it can be easily pipelined to attain a high throughput rate View full abstract»

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  • A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design

    Page(s): 1050 - 1059
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    In this paper, we propose a novel full adder design using as few as ten transistors per bit. Compared with other low-gate-count full adder designs using pass transistor logic, the proposed design features lower operating voltage, higher computing speed and lower energy (power delay product) operation. The design adopts inverter buffered xor/xnor designs to alleviate the threshold voltage loss problem commonly encountered in pass transistor logic design. This problem usually prevents the full adder design from operating in low supply voltage or cascading directly without extra buffering. The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized. The improved buffering helps the design operate under lower supply voltage compared with existing works. It also enhances the speed performance of the cascaded operation significantly while maintaining the performance edge in energy consumption. For performance comparison, both dc andperformances of the proposed design against various full adder designs are evaluated via extensive HSPICE simulations. The simulation results, based on TSMC 2P4M 0.35-mum process models, indicate that the proposed design has the lowest working Vdd and highest working frequency among all designs using ten transistors. It also features the lowest energy consumption per addition among these designs. In addition, the performance edge of the proposed design in both speed and energy consumption becomes even more significant as the word length of the adder increases View full abstract»

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  • Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder

    Page(s): 1060 - 1068
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    Although it possesses reduced computational complexity and great power saving potential, conventional adaptive Viterbi algorithm implementations contain a global best survivor path metric search operation that prevents it from being directly implemented in a high-throughput state-parallel decoder. This limitation also incurs power and silicon area overhead. This paper presents a modified adaptive Viterbi algorithm, referred to as the relaxed adaptive Viterbi algorithm, that completely eliminates the global best survivor path metric search operation. A state-parallel decoder VLSI architecture has been developed to implement the relaxed adaptive Viterbi algorithm. Using convolutional code decoding as a test vehicle, we demonstrate that state-parallel relaxed adaptive Viterbi decoders, versus Viterbi counterparts, can achieve significant power savings and modest silicon area reduction, while maintaining almost the same decoding performance and very high throughput View full abstract»

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  • A 4-kb Low-Power SRAM Design With Negative Word-Line Scheme

    Page(s): 1069 - 1076
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    The physical implementation of a prototypical 250-MHz CMOS 4-T SRAM is described in this paper. The proposed SRAM cell takes advantage of a negative word-line scheme to minimize the leakage current of the cell access transistors. As a result, the standby power consumption is drastically reduced. The proposed 4-kb 4-T SRAM is measured to consume 0.32 mW in the standby mode, and a 3.8-ns access time in the R/W mode. The highest operating clock rate is measured to be 263 MHz View full abstract»

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  • Comparative Analysis of Shift Variance and Cyclostationarity in Multirate Filter Banks

    Page(s): 1077 - 1087
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    Multirate filter banks introduce periodic time-varying phenomena into their subband signals. The nature of these effects depends on whether the signals are regarded as deterministic or as random signals. We analyze the behavior of deterministic and wide-sense stationary (WSS) random signals in multirate filter banks in a comparative manner. While aliasing in the decimation stage causes subband energy spectra of deterministic signals to become shift-variant, imaging in the interpolation stage causes WSS random signals to become WS cyclostationary (WSCS). We provide criteria to quantify both shift variance and cyclic nonstationarity. For shift variance, these criteria separately assess the shift dependence of energy and of energy spectra. Similarly for nonstationarity, they separately assess the nonstationary behavior of signal power and of power spectra. We show that, under aliasing cancellation and perfect reconstruction constraints of paraunitary and biorthogonal filter banks, these criteria evaluate the behavior of deterministic and WSS random signals in a consistent, dual way. We apply our criteria to paraunitary and biorthogonal filter banks as well as to orthogonal block transforms, and show that, for critical signals such as lines or edges in image data, the biorthogonal 9/7 filters perform best among these View full abstract»

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  • GSR: A New Genetic Algorithm for Improving Source and Channel Estimates

    Page(s): 1088 - 1098
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    In this paper, we introduce a new genetic algorithm, which allows us to refine the estimates of information source symbols and channel estimates obtained by any identification algorithm. Instead of searching the entire space, the proposed algorithm searches for the refined estimates in the subspaces near the initial estimate. Creation of initial guesses by using problem specific information and new specially tailored nonblind genetic operators, based on the ideas from schema theory, for realizing the proposed approach are described. The new genetic source symbol refinement (GSR) algorithm is tested to cope with rapidly varying finite-impulse response channels with additive noise model. The method is capable of offering fast convergence with directed search ability and exhibits a unique feature of automatic adjustment in the number of cost function evaluations with the varying signal-to-noise ratio (SNR). Computational results show that the GSR can achieve the bit-error-rate performance near to the simulated annealing bound. As compared with recent sophisticated alternatives for the problem, the GSR performance is superior over a wide range of SNR, with reduced complexity View full abstract»

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  • Circuit Theoretic Classification of Parallel Connected DC–DC Converters

    Page(s): 1099 - 1108
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    This paper describes a classification of paralleling schemes for dc-dc converters from a circuit theoretic viewpoint. The purpose is to provide a systematic classification of the types of parallel converters that can clearly identify all possible structures and control configurations, allowing simple and direct comparison of the characteristics and limitations of different paralleling schemes. In the proposed classification, converters are modeled as current sources or voltage sources, and their connection possibilities, as constrained by Kirchhoff's laws, are categorized systematically into three basic types. Moreover, control arrangements are classified according to the presence of current sharing and voltage-regulation loops. Computer simulations are presented to illustrate the characteristics of the various paralleling schemes View full abstract»

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  • Inducing Chaos in Electronic Circuits by Resonant Perturbations

    Page(s): 1109 - 1119
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    We propose a scheme to induce chaotic attractors in electronic circuits. The applications that we are interested in stipulate the following three constraints: 1) the circuit operates in a stable periodic regime far away from chaotic behavior; 2) no parameters or state variables of the circuit are directly accessible to adjustment and 3) the circuit equations are unknown and the only available information is a time series (or a signal) measured from the circuit. Under these conditions, a viable approach to chaos induction is to use external excitations such as a microwave signal, assuming that a proper coupling mechanism exists which allows the circuit to be perturbed by the excitation. The question we address in this paper is how to choose the waveform of the excitation to ensure that sustained chaos (chaotic attractor) can be generated in the circuit. We show that weak resonant perturbations with time-varying frequency and phase are generally able to drive the circuit into a hierarchy of nonlinear resonant states and eventually into chaos. We develop a theory to explain this phenomenon, provide numerical support, and demonstrate the feasibility of the method by laboratory experiments. In particular, our experimental system consists of a Duffing-type of nonlinear electronic oscillator driven by a phase-locked loop (PLL) circuit. The PLL can track the frequency and phase evolution of the target Duffing circuit and deliver resonant perturbations to generate robust chaotic attractors View full abstract»

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  • Bifurcation Analysis of PWM-1 Voltage-Mode-Controlled Buck Converter Using the Exact Discrete Model

    Page(s): 1120 - 1130
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    Nonlinear phenomena in power electronic circuits are generally studied through discrete-time maps. However, there exist very few circuit configurations (like, for example, the current-mode-controlled dc-dc converters or current programmed H-bridge inverter) for which the map can be obtained in closed form. In this paper, we show that, in a voltage-mode-controlled dc-dc converter, if the switching is governed by pulse-width modulation of the first kind (PWM-1), an explicit form of the stroboscopic map can be obtained. The resulting discrete-time state space is piecewise smooth, divided into five regions, each with a different functional form. We then analyze the bifurcation behavior using the explicit map and demonstrate the different types of border collision bifurcations that may occur in this system as a fixed point moves from one region to another. This includes the very interesting case of a direct transition from periodicity to quasi-periodicity through the route of border collision bifurcation. Mode-locking periodic windows are also obtained at certain ranges of the parameters. The two-parameter bifurcation diagram is presented, showing the domains of existence of different oscillatory modes in the system parameter plane View full abstract»

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  • New Sufficient Conditions for Global Robust Stability of Delayed Neural Networks

    Page(s): 1131 - 1141
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    In this paper, we continue to explore application of nonsmooth analysis to the study of global asymptotic robust stability (GARS) of delayed neural networks. In combination with Lyapunov theory, our approach gives several new types of sufficient conditions ensuring GARS. A significant common aspect of our results is their low computational complexity. It is demonstrated that the reported results can be verified either by conducting spectral decompositions of symmetric matrices associated with the uncertainty sets of network parameters, or by solving a semidefinite programming problem. Nontrivial examples are constructed to compare with some closely related existing results View full abstract»

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  • Positive Realness and Absolute Stability Problem of Descriptor Systems

    Page(s): 1142 - 1149
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    This paper considers a class of nonlinear descriptor systems described by a linear time-invariant descriptor system with feedback-connected sector-constrained nonlinearities. First, we discuss the positive realness problem of descriptor systems and present a new version of positive real lemma. Second, we define the notion of strongly absolute stability (SAB) which is equivalent to the linear part is regular and impulsive-free and the overall feedback system is exponential stable and a SAB criteria in frequency domain is derived. Then, we address the problem of designing a state feedback controller such that the closed-loop feedback-connected system is SAB. To achieve this, we give a linear matrix inequality (LMI)-based SAB criteria, and the above problem is converted into an LMI feasibility problem. Finally, some numerical examples are given to illustrate our approach View full abstract»

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  • Blind-Source Separation Based on Decorrelation and Nonstationarity

    Page(s): 1150 - 1158
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    In this paper, discrete-time blind-source separation (BSS) of instantaneous mixtures is studied. Decorrelation-based sufficient criteria for BSS of stationary and nonstationary sources are derived based on nonstationarity and nonwhiteness. A gradient algorithm is proposed based on these criteria. A batch-data algorithm and an on-line algorithm are developed based on the corollaries of the BSS criteria. These algorithms are especially useful for the separation of nonstationary sources. They are robust to additive white noises if the time-delayed decorrelation and the nonstationarity of the sources are considered simultaneously in the algorithms. Experiment results show the effectiveness and performance of the proposed algorithms View full abstract»

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  • 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

    Page(s): 1159
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    Freely Available from IEEE

Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras