IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 5 • May 2007

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  • Table of contents

    Publication Year: 2007, Page(s):C1 - C4
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2007, Page(s): C2
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  • Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics

    Publication Year: 2007, Page(s):817 - 833
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1083 KB) | HTML iconHTML

    Entering the nanometer era, a major challenge to current design methodologies and tools is how to effectively address the high defect densities projected for nanoelectronic technologies. To this end, a reconfiguration-based defect-avoidance methodology for defect-prone nanofabrics was proposed. It judiciously architects the nanofabric, using probabilistic considerations, such that a very large num... View full abstract»

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  • A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures

    Publication Year: 2007, Page(s):834 - 844
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    In multilevel interconnect structures, the interconnect layers are practically always perpendicular to each other. Due to the capacitive coupling between adjacent layers, the switching activity in one layer produces noise in the others. Often, this interlevel coupling noise is implicitly neglected: only the parallel neighbors of a victim line are considered noisy while the perpendicular conductors... View full abstract»

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  • Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation

    Publication Year: 2007, Page(s):845 - 857
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (802 KB) | HTML iconHTML

    This paper presents extensions of the dynamic-programming (DP) framework to consider buffer insertion and wire-sizing under effects of process variation. We study the effectiveness of this approach to reduce timing impact caused by chemical-mechanical planarization (CMP)-induced systematic variation and random Leff process variation in devices. We first present a quantitative study on t... View full abstract»

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  • Routability-Driven Placement and White Space Allocation

    Publication Year: 2007, Page(s):858 - 871
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (942 KB) | HTML iconHTML

    We present a two-stage congestion-driven placement flow. First, during each refinement stage of our multilevel global placement framework, we replace cells based on the wirelength weighted by congestion level to reduce the routing demands of congested regions. Second, after the global placement stage, we allocate appropriate amounts of white space into different regions of the chip according to a ... View full abstract»

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  • Wire Sizing for Non-Tree Topology

    Publication Year: 2007, Page(s):872 - 880
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (266 KB)

    Most existing methods for interconnect wire sizing are designed for RC trees. With the increasing popularity of the non-tree topology in clock networks and multiple link networks, wire sizing for non-tree networks becomes an important problem. In this paper, we propose the first systematic method to size the wires of general non-tree RC networks. Our method consists of three steps: 1) decompose a ... View full abstract»

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  • Two-Stage Newton–Raphson Method for Transistor-Level Simulation

    Publication Year: 2007, Page(s):881 - 895
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (825 KB)

    In this paper, we introduce an efficient transistor-level simulation tool with SPICE-accuracy for deep-submicrometer very large-scale integration circuits with strong-coupling effects. The new approach uses multigrid for huge networks of power/ground, clock, and interconnect with strong coupling. Mutual inductance can be incorporated without error-prone matrix sparsification approximations or expe... View full abstract»

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  • Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers

    Publication Year: 2007, Page(s):896 - 906
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (546 KB)

    At-speed testing is becoming crucial for modern very-large-scale-integration systems, which operate at clock speeds of hundreds of megahertz. In a scan-based test methodology, it is common to use a transition delay fault model for at-speed testing. The launching of the transition can be done either in the last cycle of scan shift [launch-off-shift (LOS)], or in a functional launch cycle that follo... View full abstract»

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  • Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration

    Publication Year: 2007, Page(s):907 - 918
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (816 KB) | HTML iconHTML

    This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10times to 40 times compres... View full abstract»

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  • Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests

    Publication Year: 2007, Page(s):919 - 931
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (661 KB) | HTML iconHTML

    Ternary content addressable memory (TCAM) plays an important role in various applications for its fast lookup operation. This paper proposes several comparison fault models (i.e., the faults cause Compare operation fail) of TCAMs based on electrical defects, such as shorts between two circuit nodes and transistor stuck-open and stuck-on faults. Two March-like tests for detecting comparison faults ... View full abstract»

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  • Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation

    Publication Year: 2007, Page(s):932 - 942
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (580 KB) | HTML iconHTML

    In this paper, we propose two fault-diagnosis methods for improving multiple-fault diagnosis resolution. The first method, based on the principle of single-fault activation and single-output observation, employs a new circuit transformation technique in conjunction with the use of a special type of diagnostic test pattern, named single-observation single-location-at-a-time (SO-SLAT) pattern. Given... View full abstract»

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  • Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics

    Publication Year: 2007, Page(s):943 - 958
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (1189 KB) | HTML iconHTML

    In this paper, a built-in self-test (BIST) procedure is proposed for testing and fault tolerance of molecular electronics-based nanofabrics. The nanofabrics are assumed to include up to 1012 devices/cm2; this requires new test strategies that can efficiently test and diagnose the nanofabrics in a reasonable time. Our BIST procedure utilizes nanofabric components as small test... View full abstract»

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  • Efficient Timing Analysis With Known False Paths Using Biclique Covering

    Publication Year: 2007, Page(s):959 - 969
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (353 KB)

    We improve the efficiency of static timing analysis when false paths are considered. The efficiency of timing analysis is critical for the performance driven optimization program because timing analysis is invoked heavily in the inner loop. However, when false paths are dealt with in timing analysis, a large number of tags needs to be created and propagated, thus deteriorating efficiency. In this ... View full abstract»

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  • A Novel γd/n RLCG Transmission Line Model Considering Complex RC(L) Loads

    Publication Year: 2007, Page(s):970 - 977
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (285 KB) | HTML iconHTML

    In deep-submicrometer integrated circuits, inductance effects have become increasingly significant, and interconnects are often modeled as transmission lines. An equivalent circuit model, which is called the gammad/n model and regularly constructed by two elementary resistance-capacitance-inductance-conductance cells, is proposed for transmission line modeling in this paper. Unlike those moment-ma... View full abstract»

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  • Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes

    Publication Year: 2007, Page(s):977 - 982
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (412 KB) | HTML iconHTML

    A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. Coding for on-chip buses requires additional bus wires and codec circuits. In this paper, fundamental bounds on the number of wires required to provide joint crosstalk avoidance and error correction using memoryless codes are presented. The authors propose ... View full abstract»

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  • High-Quality Transition Fault ATPG for Small Delay Defects

    Publication Year: 2007, Page(s):983 - 989
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract |PDF file iconPDF (201 KB) | HTML iconHTML

    A new framework is proposed to generate compact quality tests to detect small delay defects by activating and propagating transition faults only along implicitly kept sensitizable critical paths. It is shown how to implicitly generate functions to derive tests for the proposed framework. The novelty of the method relies on a multivalued algebra that is used to generate the test functions with a si... View full abstract»

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  • Special issue on multifunctional circuits and systems for future generations of wireless communications

    Publication Year: 2007, Page(s): 990
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  • 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

    Publication Year: 2007, Page(s): 991
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Information for authors

    Publication Year: 2007, Page(s): 992
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  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems society information

    Publication Year: 2007, Page(s): C3
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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Rajesh Gupta
University of California, San Diego
Computer Science and Engineering
9500 Gilman Drive
La Jolla California 92093, USA
gupta@cs.ucsd.edu