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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 9 • Date Sep 1992

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Displaying Results 1 - 13 of 13
  • An incremental zero/integer delay switch-level simulation environment

    Publication Year: 1992 , Page(s): 1131 - 1139
    Cited by:  Papers (5)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (864 KB)  

    Methods used in the implementation of an incremental zero/integer-delay switch-level logic simulator for MOS circuits based on the MOSSIM II switch-level model are presented. Zero-delay timing reduces spurious reevaluations caused by minor changes to signal timing that do not affect logic, while integer-delay timing provides an ability to model race conditions that do affect the logic. The incremental simulator is embedded within a single fully integrated capture-compile-simulate tool. Modifications to the design at any level in the structural design hierarchy are automatically mapped into (possibly many) changes in the underlying transistor netlist and the incremental simulator is triggered to quickly resimulate only the affected regions of the circuit View full abstract»

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  • The effect of placement of automatically extracted structure

    Publication Year: 1992 , Page(s): 1140 - 1152
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1104 KB)  

    A tool capable of extracting structure from a logical design was implemented, and the effect of structure on placement was studied. Results demonstrate that structure can reduce the problem complexity of a traditional placement tool when the structured portion of a design is clustered and/or seeded, thereby giving the traditional placement tool fewer cells to place. The reduction in complexity depends on the amount of structure in the logic design. In addition, placing structure may lead to better circuit performance by reducing bit-slice length, the distance a signal must travel as it traverses the combinational logic of a bit slice. The number of layer changes for clock lines and control signals can be reduced by aligning the modules connected by these signals. By strategically placing the drivers of key control signals, the lengths of their longest stubs can be reduced, thereby improving clock speed. Experiments demonstrate that structurally directed placement can reduce bit-slice length by up to 96% and clock stub length by up to 67% with negligible impact on traditional routing metrics, such as track count and wirelength View full abstract»

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  • STAR: An automatic data path allocator

    Publication Year: 1992 , Page(s): 1053 - 1064
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1120 KB)  

    The STAR package consists of three phases-preprocessing, data path construction (DPC), and data path refinement (DPR). The data structures are created and the lower limit of each area-dominant resource is determined in the preprocessing phase. In the DPC phase, the allocation is vertically divided into three subtasks: data transfer binding, operation assignment, and variable binding. Data transfers, operations and variables are grouped into clusters of manageable size, and a branch-and-bound search is performed in each cluster for each subtask. In the DPR phase, the data path is refined globally by evaluating the binding quality of each object. The contributions include: (1) a novel technique to evaluate the binding quality of an object on the basis of a sharing of hardware resources in which the object uses; (2) a method to judge the potential for upgrading a data path; and (3) an iterative improvement technique based on the idea of a relation network and state transition View full abstract»

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  • Probabilistic analysis and algorithms for reconfiguration of memory arrays

    Publication Year: 1992 , Page(s): 1153 - 1160
    Cited by:  Papers (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (652 KB)  

    Reconfiguration of memory arrays with spare rows and columns has been shown to be an NP-complete problem. An analysis of average-case time complexities of several existing heuristics is presented, as well as a provably average-case polynomial-time algorithm for reconfiguration of memories with spare rows and columns. The algorithm runs faster than previous heuristics when the problem size is larger View full abstract»

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  • Dynamic and static load balancing for solving block bordered circuit equations on multiprocessors

    Publication Year: 1992 , Page(s): 1086 - 1094
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB)  

    A special class of large-scale nonlinear systems of equations of block bordered structure is generated in VLSI circuit simulation from the sparse and irregular nature of the circuit matrices. Several Newton-like parallel methods for solving the block bordered equations are presented. Static and dynamic load balancing problems that arise in solving the circuit equations on multiprocessors are discussed. Computational results obtained using the BBN GP1000, a shared memory multiprocessor through a distributed architecture, are presented to show the effectiveness of dynamic and static load balancing. These experiments include a simulation of the op-amp 741 amplifier and a large analog filter simulation that leads to a multilevel block bordered system of nonlinear equations View full abstract»

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  • Optimal diagnostic methods for wiring interconnects

    Publication Year: 1992 , Page(s): 1161 - 1166
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (544 KB)  

    The problem of generating minimum test sets for diagnosing faults in wiring interconnects on printed circuit boards is addressed. It is assumed that all the nets can be accessed in parallel or through a boundary-scan chain on the board. The fault model includes multiple stuck-at-hand faults. Three methods for three different diagnosis mechanisms are presented. All the diagnostic methods can be further improved by taking advantage of the structural information of wiring interconnects View full abstract»

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  • A novel geometric resizing technique for data conversion from CAD data to electron beam exposure data

    Publication Year: 1992 , Page(s): 1104 - 1113
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (880 KB)  

    A novel resizing algorithm, based on the effective use of the hierarchical structure of CAD data, is proposed to speed up the conversion time for CAD data conversion into electron beam exposure data. Resizing can be performed even for overlap between cells, which has been usually allowed in CAD data and has interrupted the hierarchical treatment in the data conversion, by introducing three key techniques: cut and abandon, link mark, and null edge. The total conversion time of a 13 K-gate LSI circuit is improved by a factor of 3.8, with the shape handling time by a factor of 5.1, compared with a conventional method. Experimental results show that overhead can be ignored by introducing the new techniques in hierarchical treatment View full abstract»

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  • Two new techniques for unit-delay compiled simulation

    Publication Year: 1992 , Page(s): 1120 - 1130
    Cited by:  Papers (11)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1012 KB)  

    The potential change (PC)-set method and the parallel technique for generating compiled unit-delay simulators for acrylic circuits are discussed. The PC-set method analyzes the network, determines the set of potential change times for each net, and generates gate simulations for each potential change. The parallel technique, which is based on the concept of bit-parallel simulation is faster and generates less code than the PC-set method, but it is not amenable to data-parallel simulation of multiple input vectors. Both techniques are based on the well-known levelization algorithm used to generate zero-delay levelized compiled code simulation. Two optimizations of the basic parallel technique are presented, called bit-field trimming and shift elimination. Performance results using the ISCAS 85 benchmarks show a factor-of-four improvement for the PC-set method and a factor-of-ten improvement for the parallel technique. The optimization schemes show an average performance improvement of 47% over the unoptimized simulations View full abstract»

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  • A mobility model including the screening effect in MOS inversion layer

    Publication Year: 1992 , Page(s): 1114 - 1119
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    A mobility model for MOSFET device simulation is proposed. The model is not only applicable to both inversion layer and source/drain high concentration regions of a MOSFET, but it also takes into account the screening effect in the inversion layer. The model also includes an improved normal-field dependence for thin gate oxide MOSFETs. The low parallel electric field mobility is estimated by adding mobilities due to donor scattering, acceptor scattering and lattice scattering using Matthiesen's rule. Mobilities due to both the donor and the acceptor scattering include the electron screening effect. The mobility due to lattice scattering is formed as a function of normal electric field En, including the strong dependence term of E n, to express surface roughness scattering. Calculation results of the device simulation using the mobility model show good agreement with the experimental data for various channel dopings View full abstract»

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  • New spectral methods for ratio cut partitioning and clustering

    Publication Year: 1992 , Page(s): 1074 - 1085
    Cited by:  Papers (112)  |  Patents (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1084 KB)  

    Partitioning of circuit netlists in VLSI design is considered. It is shown that the second smallest eigenvalue of a matrix derived from the netlist gives a provably good approximation of the optimal ratio cut partition cost. It is also demonstrated that fast Lanczos-type methods for the sparse symmetric eigenvalue problem are a robust basis for computing heuristic ratio cuts based on the eigenvector of this second eigenvalue. Effective clustering methods are an immediate by-product of the second eigenvector computation and are very successful on the difficult input classes proposed in the CAD literature. The intersection graph representation of the circuit netlist is considered, as a basis for partitioning, a heuristic based on spectral ratio cut partitioning of the netlist intersection graph is proposed. The partitioning heuristics were tested on industry benchmark suites, and the results were good in terms of both solution quality and runtime. Several types of algorithmic speedups and directions for future work are discussed View full abstract»

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  • A functional fault model for sequential machines

    Publication Year: 1992 , Page(s): 1065 - 1073
    Cited by:  Papers (31)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (840 KB)  

    A fault model at the state transition level is proposed for finite state machines. In this model, a fault causes the destination state of a state transition to be faulty. Analysis shows that a test set that detects all single-state-transition (SST) faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. The quality of the test set generated for SST faults is close to that of the sequences derived from the checking experiment. It is also shown that the upper bound of the length of the SST fault test is 2 MN2 for an N-state M-transition machine, while that of the checking sequence is exponential. An automatic test generation algorithm and a test generation system, FTG, based on the model show that the test set generated for SST faults achieves high single stuck-at-fault coverage as well as high transistor fault coverage for multilevel implementations of the machine View full abstract»

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  • Hierarchical Steiner tree construction in uniform orientations

    Publication Year: 1992 , Page(s): 1095 - 1103
    Cited by:  Papers (20)  |  Patents (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (752 KB)  

    A hierarchical approach to Steiner tree construction in λ-geometry is proposed. The algorithm runs in time O(n log n) and the length of the constructed tree is at most [σ/cos(π/2λ)] times (for λ=2, 3/2 times) the length of the optimal Steiner tree where n is the cardinality of the point set and it was recently proved that σ is (2/√3). How to trade off between the running time of the algorithm and the length of the produced Steiner tree is shown. Given enough time, an optimal Steiner tree will be obtained. The algorithm is extended to construct a Steiner tree of a set of subtrees (i.e., partial trees) and runs in ON log N) time, where N is the total number of edges of the subtrees View full abstract»

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  • Heuristic minimization of Boolean relations using testing techniques

    Publication Year: 1992 , Page(s): 1166 - 1172
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (608 KB)  

    A Boolean relation is a one-to-many multioutput Boolean mapping and is a generalization of incompletely specified logic functions. Boolean relations arise in several contexts (for instance, in a finite state machine with sets of equivalent states). Minimization of Boolean relations is important from the point of view of synthesis, especially synthesis for testability. A fast heuristic procedure for finding an optimal sum-of-products representation for a function compatible with a Boolean relation is described. Starting with an initial function compatible with the relation, a process of iterative logic improvement based on test generation techniques is used to derive a minimal function View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu