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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 9 • Date Sep 1992

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Displaying Results 1 - 13 of 13
  • Probabilistic analysis and algorithms for reconfiguration of memory arrays

    Publication Year: 1992, Page(s):1153 - 1160
    Cited by:  Papers (16)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (652 KB)

    Reconfiguration of memory arrays with spare rows and columns has been shown to be an NP-complete problem. An analysis of average-case time complexities of several existing heuristics is presented, as well as a provably average-case polynomial-time algorithm for reconfiguration of memories with spare rows and columns. The algorithm runs faster than previous heuristics when the problem size is large... View full abstract»

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  • The effect of placement of automatically extracted structure

    Publication Year: 1992, Page(s):1140 - 1152
    Cited by:  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1104 KB)

    A tool capable of extracting structure from a logical design was implemented, and the effect of structure on placement was studied. Results demonstrate that structure can reduce the problem complexity of a traditional placement tool when the structured portion of a design is clustered and/or seeded, thereby giving the traditional placement tool fewer cells to place. The reduction in complexity dep... View full abstract»

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  • An incremental zero/integer delay switch-level simulation environment

    Publication Year: 1992, Page(s):1131 - 1139
    Cited by:  Papers (5)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (864 KB)

    Methods used in the implementation of an incremental zero/integer-delay switch-level logic simulator for MOS circuits based on the MOSSIM II switch-level model are presented. Zero-delay timing reduces spurious reevaluations caused by minor changes to signal timing that do not affect logic, while integer-delay timing provides an ability to model race conditions that do affect the logic. The increme... View full abstract»

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  • Two new techniques for unit-delay compiled simulation

    Publication Year: 1992, Page(s):1120 - 1130
    Cited by:  Papers (13)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1012 KB)

    The potential change (PC)-set method and the parallel technique for generating compiled unit-delay simulators for acrylic circuits are discussed. The PC-set method analyzes the network, determines the set of potential change times for each net, and generates gate simulations for each potential change. The parallel technique, which is based on the concept of bit-parallel simulation is faster and ge... View full abstract»

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  • Hierarchical Steiner tree construction in uniform orientations

    Publication Year: 1992, Page(s):1095 - 1103
    Cited by:  Papers (39)  |  Patents (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    A hierarchical approach to Steiner tree construction in λ-geometry is proposed. The algorithm runs in time O(n log n) and the length of the constructed tree is at most [σ/cos(π/2λ)] times (for λ=2, 3/2 times) the length of the optimal Steiner tree where n is the cardinality of the point set and it was recently proved that σ is... View full abstract»

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  • STAR: An automatic data path allocator

    Publication Year: 1992, Page(s):1053 - 1064
    Cited by:  Papers (29)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1120 KB)

    The STAR package consists of three phases-preprocessing, data path construction (DPC), and data path refinement (DPR). The data structures are created and the lower limit of each area-dominant resource is determined in the preprocessing phase. In the DPC phase, the allocation is vertically divided into three subtasks: data transfer binding, operation assignment, and variable binding. Data transfer... View full abstract»

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  • Heuristic minimization of Boolean relations using testing techniques

    Publication Year: 1992, Page(s):1166 - 1172
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (608 KB)

    A Boolean relation is a one-to-many multioutput Boolean mapping and is a generalization of incompletely specified logic functions. Boolean relations arise in several contexts (for instance, in a finite state machine with sets of equivalent states). Minimization of Boolean relations is important from the point of view of synthesis, especially synthesis for testability. A fast heuristic procedure fo... View full abstract»

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  • A mobility model including the screening effect in MOS inversion layer

    Publication Year: 1992, Page(s):1114 - 1119
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (516 KB)

    A mobility model for MOSFET device simulation is proposed. The model is not only applicable to both inversion layer and source/drain high concentration regions of a MOSFET, but it also takes into account the screening effect in the inversion layer. The model also includes an improved normal-field dependence for thin gate oxide MOSFETs. The low parallel electric field mobility is estimated by addin... View full abstract»

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  • Dynamic and static load balancing for solving block bordered circuit equations on multiprocessors

    Publication Year: 1992, Page(s):1086 - 1094
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (768 KB)

    A special class of large-scale nonlinear systems of equations of block bordered structure is generated in VLSI circuit simulation from the sparse and irregular nature of the circuit matrices. Several Newton-like parallel methods for solving the block bordered equations are presented. Static and dynamic load balancing problems that arise in solving the circuit equations on multiprocessors are discu... View full abstract»

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  • Optimal diagnostic methods for wiring interconnects

    Publication Year: 1992, Page(s):1161 - 1166
    Cited by:  Papers (22)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (544 KB)

    The problem of generating minimum test sets for diagnosing faults in wiring interconnects on printed circuit boards is addressed. It is assumed that all the nets can be accessed in parallel or through a boundary-scan chain on the board. The fault model includes multiple stuck-at-hand faults. Three methods for three different diagnosis mechanisms are presented. All the diagnostic methods can be fur... View full abstract»

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  • A novel geometric resizing technique for data conversion from CAD data to electron beam exposure data

    Publication Year: 1992, Page(s):1104 - 1113
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (880 KB)

    A novel resizing algorithm, based on the effective use of the hierarchical structure of CAD data, is proposed to speed up the conversion time for CAD data conversion into electron beam exposure data. Resizing can be performed even for overlap between cells, which has been usually allowed in CAD data and has interrupted the hierarchical treatment in the data conversion, by introducing three key tec... View full abstract»

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  • A functional fault model for sequential machines

    Publication Year: 1992, Page(s):1065 - 1073
    Cited by:  Papers (43)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (840 KB)

    A fault model at the state transition level is proposed for finite state machines. In this model, a fault causes the destination state of a state transition to be faulty. Analysis shows that a test set that detects all single-state-transition (SST) faults will also detect most multiple-state-transition (MST) faults in practical finite state machines. The quality of the test set generated for SST f... View full abstract»

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  • New spectral methods for ratio cut partitioning and clustering

    Publication Year: 1992, Page(s):1074 - 1085
    Cited by:  Papers (154)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1084 KB)

    Partitioning of circuit netlists in VLSI design is considered. It is shown that the second smallest eigenvalue of a matrix derived from the netlist gives a provably good approximation of the optimal ratio cut partition cost. It is also demonstrated that fast Lanczos-type methods for the sparse symmetric eigenvalue problem are a robust basis for computing heuristic ratio cuts based on the eigenvect... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu