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IEE Proceedings E - Computers and Digital Techniques

Issue 5 • Date Sep 1992

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Displaying Results 1 - 12 of 12
  • New fast fixed-delay sizing algorithm for high-performance CMOS combinational logic circuits and its applications

    Publication Year: 1992, Page(s):379 - 386
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (464 KB)

    A sizing methodology called the near-characteristic waveform-synthesising method (NCWSM) is proposed to determine the device sizes of CMOS combinational logic circuits under a fixed delay specification. By using accurate physical timing models and the NCWSM, a fixed-delay sizing algorithm is developed and implemented, which sizes circuits quickly and globally. It can handle CMOS inverters, multi-i... View full abstract»

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  • Distance measure for attributed fuzzy tournaments

    Publication Year: 1992, Page(s):373 - 378
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (396 KB)

    Attributed fuzzy tournaments (AFTs) are a special type of attributed fuzzy graph that are useful to represent uncertainties inherent to many real-world problems. A new distance measure between two AFTs is defined. Useful applications of the proposed distance measure can be found in scene matching, where the nodes of an AFT represent the objects in the scene and the arcs represent the relationships... View full abstract»

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  • MARS: a RISC based multiple function units Lisp machine

    Publication Year: 1992, Page(s):410 - 420
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (784 KB)

    This paper focuses on the features and evaluation of the processor board architecture of MARS with special emphasis on Lisp processing. Inside the processor board, there are four processing units, namely, the instruction fetch unit (IFU), integer processing unit (IPU), floating-point processing unit (FPU) and list processing unit (LPU). The IFU feeds instructions to the processing units and suppor... View full abstract»

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  • Binary decision based representation implementation of sequential systems

    Publication Year: 1992, Page(s):450 - 456
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (388 KB)

    Two methods of binary decision based representation and implementation of asynchronous sequential systems are considered. A method of state assignment for the binary decision based system is presented. The method is based on the weights of the test variables and their effect on BD graph complexity. View full abstract»

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  • Inversion of integer matrices in residue number system

    Publication Year: 1992, Page(s):465 - 468
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (244 KB)

    The presented algorithm makes use of the recently introduced incompletely specified residue number system. This system enables the operations necessary in the inversion process to be done quickly, completely in parallel for different moduli, even if divisors and some system moduli are not relatively prime. The algorithm guarantees the result correctness and the only condition for its applicability... View full abstract»

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  • Asynchronous transfer-mode receiver

    Publication Year: 1992, Page(s):401 - 409
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (652 KB)

    Asynchronous cell-based transmission is the preferred transmission mode for emerging high-speed network standards such as the IEEE 802.6 metropolitan-area-network standard and the CCITT broadband integrated services digital network. These networks are envisaged to operate at bit rates in excess of 100 Mbit/s. The high bit rate and the cell-based mode of transmission pose challenging requirements o... View full abstract»

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  • iHARP: a multiple instruction issue processor

    Publication Year: 1992, Page(s):439 - 449
    Cited by:  Papers (4)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (744 KB)

    Recently, multiple instruction issue architectures have attempted to improve processor performance by fetching and dispatching more than one instruction in each processor cycle. This paper describes iHARP, a multiple instruction issue processor chip, which is currently being developed at Hatfield Polytechnic. The objective of the HARP project is to develop a processor which will execute nonnumeric... View full abstract»

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  • Universal architecture for matrix transposition

    Publication Year: 1992, Page(s):387 - 392
    Cited by:  Papers (6)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (460 KB)

    A new real-time architecture for matrix transposition is presented. This architecture exploits the inherent parallelism and pipelining of the transposition operation resulting in an efficient mapping of the operation (algorithm) onto the structure. More importantly, this architecture is a universal implementation of executing matrix transposition because it allows data to flow in and out of the st... View full abstract»

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  • Methods for detection of some properties of multiple-valued functions

    Publication Year: 1992, Page(s):421 - 429
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (552 KB)

    Methods are given for some symmetry properties: detection and functional decomposition of multiple-valued functions. Both methods are formulated using a matrix notation which enables the fast algorithms for their implementation to be disclosed. The problem of optimisation in logic design can be considered with respect to a number of different criteria. However, in general, all of them finally can ... View full abstract»

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  • A new partial scan design based on hard fault distribution analysis

    Publication Year: 1992, Page(s):457 - 463
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (452 KB)

    A post-test generation partial scan method, called hard fault distribution (HFD), is proposed. The goals of this approach are to have the ability of co-operating with any test pattern generator and to obtain maximum fault coverage for the number of flip-flops selected to be scanned. The concept of HFD method consists of the essence of previous relative works such as testability analysis, structure... View full abstract»

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  • Performance of signature registers in the presence of correlated errors

    Publication Year: 1992, Page(s):393 - 400
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (468 KB)

    In signature analysis, aliasing is usually examined under the independent or the q-ary symmetric error model. In contrast to the independent error model, the q-ary error model assumes space correlation among outputs. However, both independent and q-ary error models assume that the errors resulting from consecutive test vectors are independent over time. This assumption is reasonable for combinatio... View full abstract»

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  • Static performance of a divide-and-conquer information-distribution protocol supporting a load-balancing scheme

    Publication Year: 1992, Page(s):430 - 438
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (712 KB)

    The paper examines an application of the divide-and-conquer approach to information collection and dissemination in distributed systems. The general approach is to divide the system into subsystems, distribute information within the subsystems, and distribute information between the subsystems. Distributed decisions are made as a result of the system-wide migration of information. The implementati... View full abstract»

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