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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 5 • Date May 2007

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  • Table of contents

    Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Page(s): C2
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  • A Compact and Low-Power CMOS Circuit for Fully Integrated NEMS Resonators

    Page(s): 377 - 381
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    This brief presents a fully integrated nanoelectromechanical system (NEMS) resonator, operable at frequencies in the megahertz range, together with a compact built-in CMOS interfacing circuitry. The proposed low-power second-generation current conveyor circuit allows detailed read-out of the nanocantilever structure for either extraction of equivalent circuit models or comparative studies at different pressure and dc biasing conditions. In this sense, extensive experimental results are presented for a real mixed electromechanical system integrated through a combination of in-house standard CMOS technology and nanodevice post-processing by nanostencil lithography. The proposed read-out scheme can be easily adapted to operate the nanocantilever in closed loop operation as a stand-alone NEMS oscillator View full abstract»

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  • Improved Reversed Nested Miller Frequency Compensation Technique With Voltage Buffer and Resistor

    Page(s): 382 - 386
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    This brief introduces and develops a novel frequency compensation technique for three-stage operational transconductance amplifiers. The new compensation topology exploits a voltage buffer and a nulling resistor to achieve a double pole-zero cancellation, occurring beyond the gain-bandwidth product. To verify the effectiveness of the compensation scheme, an amplifier has been fabricated in a standard 0.5-mum CMOS process. Experimental measurements are found to be in good agreement with the theoretical analysis and show an improvement in small-signal and large-signal performances View full abstract»

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  • Estimation of Aliasing Effects Due to Periodical Nonuniform Individual Sampling in High-Q Switched-Capacitor Filters

    Page(s): 387 - 391
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    The periodical nonuniform individual sampling scheme has been shown suitable for capacitance spread and total capacitor area reduction in high quality (Q) factor switched-capacitor (SC) filters. However, the use of periodical nonuniform clock signals results in additional aliasing components in the output spectrum. This paper presents a simple model to analyze the generation of such alias components and gives practical expressions to estimate their power. The results are verified through circuit simulation of a 10.7-MHz second-order SC bandpass filter in a 0.35-mum CMOS technology. Implications on the use of this technique in the design of intermediate-frequency filters are discussed View full abstract»

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  • A First-Order Tree-Structured DAC With Reduced Signal-Band Noise

    Page(s): 392 - 396
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    A mismatch-shaping tree-structured digital-to-analog converter (DAC) utilizes several layers of switching blocks to spectrally shape the DAC circuit errors. A first-order mismatch-shaping DAC using un-dithered switching sequences for the switching blocks results in spurious tones in the DAC noise. The unwanted tones can be eliminated from the DAC noise by employing white dither sequences to randomly select two types of short root symbols to be placed in the switching sequences. Dithered switching sequences, unfortunately, result in a higher noise floor in the DAC noise, in comparison with un-dithered switching sequences. In this brief, we propose an improved first-order sequencing logic to eliminate unwanted tones while causing only a modest increase in the in-band noise floor at a very modest hardware cost. Our mismatch-shaping sequencing logic is based on the scheme using a white dither sequence to randomly select each symbol between two specific types of long root symbols. Alternatively, our scheme can be viewed as using a high-pass dither sequence to randomly select the short root symbols. An analytical formula for the power-spectral density of the proposed switching sequence is presented to show its improvement over the prior first-order switching sequence. It is also shown from numerical simulations that the proposed switching sequence improves the signal-to-noise plus distortion ratio by more than 5 dB for a sigma-delta modulator with static DAC-element errors chosen from a Gaussian distribution with a standard deviation of 1% View full abstract»

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  • A 100-dB CMRR CMOS Operational Amplifier With Single-Supply Capability

    Page(s): 397 - 401
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    A CMOS operational amplifier that has a common-mode rejection ratio (CMRR), a power-supply rejection ratio (PSRR), and gain above 100 dB for each of these parameters is described. This is achieved by combining a high output-impedance tail current source with a stable drain-source voltage of the input transistors. The common-mode input signal range includes the negative rail. This is obtained by controlling the bulk bias of the input and cascoding transistors. The amplifier consists of two gain stages connected via cascoded current mirrors. The gain is improved by using gain boost in the current mirrors, and by the suppression of impact ionization current in the output stage View full abstract»

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  • An Injection-Locked Frequency-Tracking Σ∆ Direct Digital Frequency Synthesizer

    Page(s): 402 - 406
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (713 KB) |  | HTML iconHTML  

    A bandpass (BP) sigma-delta modulator (SigmaDeltaM)-based direct digital frequency synthesizer (DDS) architecture is presented. The DDS output is passed through a single-bit, second-order BPSigmaDeltaM, shaping quantization noise out of the signal band. The single-bit BPSigmaDeltaM is then injection locked to an LC-tank oscillator, which provides a tracking BP filter response within its locking range, suppressing the BPSigmaDeltaM out of band quantization noise. The instantaneous digital frequency control word input of the DDS is used to tune the noise shaper center frequency, achieving up to 20% tuning range around the fundamental. The BPSigmaDeltaM-based synthesizer is fabricated in a 0.25-mum digital CMOS process with four layers of metal. With a second-order BP noise shaper and a 44-MHz LC tank oscillator, an SFDR of 73 dB at a 2-MHz bandwidth and phase noise lower than -105 dBc/Hz at a 10-kHz offset is achieved View full abstract»

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  • CMOS Latch Using Quad for High-Speed Comparators

    Page(s): 407 - 411
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    The well-known CMOS quad consisting of two asymmetric differential pairs is a transconductance element. It provides an additional output current proportional to the square of its differential input voltage. Here, we use both the linear and square-law outputs of a quad to build a high-speed latch that has differential low-voltage output swing. This latch retains the useful property of constant power-supply current like all current-biased differential current-mode logic circuits. Simulation results for 0.18-mum CMOS process are presented. The design is application specific and is intended for use in high-speed comparators needed for analog-to-digital converters View full abstract»

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  • A High-Performance Elliptic Curve Cryptographic Processor for General Curves Over GF(p) Based on a Systolic Arithmetic Unit

    Page(s): 412 - 416
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    This brief presents a high-performance elliptic curve cryptographic processor for general curves over GF(p), which features a systolic arithmetic unit. We propose a new unified systolic array that efficiently implements addition, subtraction, multiplication and division over GF(p). At the system level, the control dependencies in the operation sequence and the mismatched communication between the systolic array and the separate storage would stall the pipeline in the systolic array. These pipeline stalls are successfully avoided by using two optimization methods. Synthesized in 0.13-mum standard-cell technology, the processor requires 1.01 ms to compute a 256-bit scalar multiplication for general curves over GF(p) View full abstract»

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  • Design Strategy for Step-Up Charge Pumps With Variable Integer Conversion Ratios

    Page(s): 417 - 421
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (610 KB) |  | HTML iconHTML  

    Method in identifying all possible configurations of 2-phase charge pumps giving an integer conversion ratio with a fixed number of flying capacitors is presented. A systematic strategy is proposed to design an integrated charge pump as an example with a variable gain of 6times and 7times in a standard 0.35-mum CMOS process using only 4 flying capacitors. Conduction loss is considered and minimized. Measurement results verified the validity of the design methodology View full abstract»

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  • Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Packet Transform

    Page(s): 422 - 426
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    This brief presents a novel very large-scale integration (VLSI) architecture for discrete wavelet packet transform (DWPT). By exploiting the in-place nature of the DWPT algorithm, this architecture has an efficient pipeline structure to implement high-throughput processing without any on-chip memory/first-in first out access. A folded architecture for lifting-based wavelet filters is proposed to compute the wavelet butterflies in different groups simultaneously at each decomposition level. According to the comparison results, the proposed VLSI architecture is more efficient than the previous proposed architectures in terms of memory access, hardware regularity and simplicity, and throughput. The folded architecture not only achieves a significant reduction in hardware cost but also maintains both the hardware utilization and high-throughput processing with comparison to the direct mapped tree-structured architecture View full abstract»

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  • Least-Squares Design of FIR Filters Based on a Compacted Feedback Neural Network

    Page(s): 427 - 431
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    The design of finite-impulse response (FIR) filters can be performed by using neural networks by formulating the objective function to a Lyapunov energy function. Focusing on this goal, the authors present an improved structure of a feedback neural network to implement the least-squares design of FIR filters. In addition to using the closed-form expressions for the synaptic weight matrix and the bias parameter of the Hopfield neural network (HNN), the proposed approach can achieve a notable reduction both in the amount of computation required and hardware complexity compared to the previous neural-based method. Simulation results indicate the effectiveness of the proposed approach View full abstract»

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  • Counterexamples to a Method for Identifying Hopf Bifurcations Without Eigenvalue Calculation

    Page(s): 432 - 434
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    We give counterexamples to the numerical method for detecting Hopf bifurcations in electric power systems by singularity of a symmetrized Jacobian in Y. Zhou, V. Ajjarapu," A fast algorithm for identification and tracing of voltage and oscillatory stability margin boundaries", IEEE Proceedings, vol.93, no.5, May 2005, p.934-46. The counterexamples include some simple matrix examples and a single machine infinite bus power system View full abstract»

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  • Phase Diffusion Coefficient for Oscillators Perturbed by Colored Noise

    Page(s): 435 - 439
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    The phase diffusion coefficient and the mean frequency of a two-dimensional nonlinear oscillator perturbed by colored noise is theoretically predicted and compared with numerical simulations of the Langevin system. At high oscillator frequencies, the first-order perturbation approximation of Demir is observed to yield inaccurate results for the phase diffusion coefficient when the spectrum of the noise sources decay faster than omega-2. A novel asymptotic approach which describes the diffusion coefficient in such instances is developed View full abstract»

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  • Cellular Neural Networks With Transient Chaos

    Page(s): 440 - 444
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (181 KB) |  | HTML iconHTML  

    A new model of cellular neural networks (CNNs) with transient chaos is proposed by adding negative self-feedbacks into CNNs after transforming the dynamic equation to discrete time via Euler's method. The simulation on the single neuron model shows stable fix points, bifurcation and chaos. Hence, this new CNN model has richer and more flexible dynamics, and therefore may possess better capabilities of solving various problems, compared to the conventional CNN with only stable dynamics View full abstract»

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  • Real-Time Dynamic Voltage Loop Scheduling for Multi-Core Embedded Systems

    Page(s): 445 - 449
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    In this brief, we propose a novel real-time loop-scheduling technique to minimize energy consumption via dynamic voltage scaling (DVS) for applications with loops considering transition overhead. One algorithm, dynamic voltage loop scheduling (DVLS), is designed integrating with DVS. In DVLS, we repeatedly regroup a loop based on rotation scheduling and decrease the energy by DVS as much as possible within a timing constraint. We conduct the experiments on a set of digital signal processing benchmarks. The experimental results show that DVLS achieves big energy saving compared with the traditional time-performance-oriented scheduling algorithm View full abstract»

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  • Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture

    Page(s): 450 - 454
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    A two-stage scan architecture is proposed to constrain transition propagation within a small part of scan flip-flops. Most scan flip-flops are deactivated during test application. The first stage includes multiple scan chains, where each scan chain is driven by a primary input. Each scan flip-flop in the multiple scan chains drives a group of scan flip-flops in the second stage. Scan flip-flops in different stages use separate clock signals. Test signals assigned to scan flip-flops in the multiple scan chains are applied to the scan flip-flops of the second stage in one clock cycle after the test vector has been applied to the multiple scan chains. There exists no transition at the scan flip-flops in the second stage when a test vector is applied to the multiple scan chains View full abstract»

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  • Robust Stability of Uncertain Discrete Impulsive Systems

    Page(s): 455 - 459
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    This brief studies uncertain discrete impulsive systems. The robustly asymptotical stability criteria are established for linear discrete impulsive system and a class of uncertain nonlinear discrete impulsive systems, respectively. These stability criteria are expressed in terms of fairly simple algebraic conditions so that they are easy to be tested. Some examples are given to illustrate results obtained by us View full abstract»

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  • Clock-Logic Domino Circuits for High-Speed and Energy-Efficient Microprocessor Pipelines

    Page(s): 460 - 464
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    We present a design methodology for synchronous single-rail domino logic circuits, where inverting and nonmonotonic logic functions can be integrated into a pipeline with almost zero overhead relative to classic domino counterparts. This logic family, called clock-logic (CL) domino, is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL domino algorithmic logic unit (ALU) at 1 GHz under high skew conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required View full abstract»

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  • Special issue on multifunctional circuits and systems for future generations of wireless communications

    Page(s): 465
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  • 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

    Page(s): 466
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  • Explore IEL IEEE's most comprehensive resource [advertisement]

    Page(s): 467
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs Information for authors

    Page(s): 468
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  • IEEE Circuits and Systems Society Information

    Page(s): C3
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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope