Proceedings of the IEEE

Issue 3 • March 2007

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Displaying Results 1 - 19 of 19
  • [Front cover]

    Publication Year: 2007, Page(s): C1
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  • Proceedings of the IEEE publication information

    Publication Year: 2007, Page(s):C1 - C2
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  • Table of contents

    Publication Year: 2007, Page(s):461 - 462
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  • Biological Inspiration in the Design of Computing Systems

    Publication Year: 2007, Page(s):463 - 464
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  • Special Issue on Leading-Edge Computer Aided Design Solutions for Advanced Digital and Mixed-Signal Systems-on-Chips

    Publication Year: 2007, Page(s):465 - 466
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  • Quo Vadis, SLD? Reasoning About the Trends and Challenges of System Level Design

    Publication Year: 2007, Page(s):467 - 506
    Cited by:  Papers (147)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1037 KB) | HTML iconHTML

    System-level design (SLD) is considered by many as the next frontier in electronic design automation (EDA). SLD means many things to different people since there is no wide agreement on a definition of the term. Academia, designers, and EDA experts have taken different avenues to attack the problem, for the most part springing from the basis of traditional EDA and trying to raise the level of abst... View full abstract»

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  • Computer-Aided Design for Low-Power Robust Computing in Nanoscale CMOS

    Publication Year: 2007, Page(s):507 - 529
    Cited by:  Papers (8)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (741 KB) | HTML iconHTML

    This work argues that the foremost challenges to the continued rapid improvements in CMOS integrated circuit (IC) performance are power consumption and design robustness. Furthermore, these two goals are often contradictory in nature, which indicates that joint optimization approaches must be adopted to properly handle both. To highlight needs in computer-aided design (CAD), we review a sampling o... View full abstract»

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  • Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM

    Publication Year: 2007, Page(s):530 - 554
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (902 KB) | HTML iconHTML

    IBM's high-performance microprocessor designs leverage internally developed electronic design automation tools to create high-frequency, power efficient, and robust microprocessors. This paper describes some of the tools employed in the custom circuit design methodology in IBM. The tools described include a transistor-level block-based static timer, a static noise analysis methodology, and a trans... View full abstract»

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  • BonnTools: Mathematical Innovation for Layout and Timing Closure of Systems on a Chip

    Publication Year: 2007, Page(s):555 - 572
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (800 KB) | HTML iconHTML

    The BonnTools provide innovative solutions for layout and timing closure that are used for many of the most complex integrated circuits. During 20 years of cooperation between the University of Bonn and IBM, new mathematical foundations and algorithms have been developed for the need of new technologies and leading-edge designs. In this paper we present the main ideas for placement, routing, timin... View full abstract»

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  • Techniques for Fast Physical Synthesis

    Publication Year: 2007, Page(s):573 - 599
    Cited by:  Papers (30)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1384 KB) | HTML iconHTML

    The traditional purpose of physical synthesis is to perform timing closure , i.e., to create a placed design that meets its timing specifications while also satisfying electrical, routability, and signal integrity constraints. In modern design flows, physical synthesis tools hardly ever achieve this goal in their first iteration. The design team must iterate by studying the output of the physical ... View full abstract»

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  • Fundamentals of Fast Simulation Algorithms for RF Circuits

    Publication Year: 2007, Page(s):600 - 621
    Cited by:  Papers (26)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (637 KB) | HTML iconHTML

    Designers of RF circuits such as power amplifiers, mixers, and filters make extensive use of simulation tools which perform periodic steady-state analysis and its extensions, but until the mid 1990s, the computational costs of these simulation tools restricted designers from simulating the behavior of complete RF subsystems. The introduction of fast matrix-implicit iterative algorithms completely ... View full abstract»

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  • Verification of Complex Analog and RF IC Designs

    Publication Year: 2007, Page(s):622 - 639
    Cited by:  Papers (17)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1336 KB) | HTML iconHTML

    Meeting performance specifications in the design of analog and RF (A/RF) blocks and integrated circuits (IC) continues to require a high degree of skill, creativity, and expertise. However, today's A/RF designers are increasingly faced with a new challenge. Functional complexity in terms modes of operation, extensive digital calibration, and architectural algorithms is now overwhelming traditional... View full abstract»

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  • Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs

    Publication Year: 2007, Page(s):640 - 669
    Cited by:  Papers (92)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1777 KB) | HTML iconHTML

    The paper describes the recent state of the art in hierarchical analog synthesis, with a strong emphasis on associated techniques for computer-aided model generation and optimization. Over the past decade, analog design automation has progressed to the point where there are industrially useful and commercially available tools at the cell level-tools for analog components with 10-100 devices. Autom... View full abstract»

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  • An Integrated CAD Methodology for Evaluating MOSFET and Parasitic Extraction Models and Variability

    Publication Year: 2007, Page(s):670 - 687
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1583 KB) | HTML iconHTML

    An integrated computer-aided design (CAD) framework for evaluating MOSFET and layout parasitic extraction (LPE) models and circuit simulators used in the timing and power analysis of CMOS products is presented. This unified CAD methodology builds a step-wise understanding of the underlying parameter values in the models and their impact on circuit performance. A number of circuit experiments are i... View full abstract»

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  • Electrical Engineering Hall of Fame: Stanford C. Hooper

    Publication Year: 2007, Page(s):688 - 692
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  • Future Special Issues/Special Sections of the Proceedings

    Publication Year: 2007, Page(s):693 - 694
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  • IEEE copyright form

    Publication Year: 2007, Page(s):695 - 696
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  • Put your technology leadership in writing

    Publication Year: 2007, Page(s): C3
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  • Coming in February the Proceedings of the IEEE

    Publication Year: 2007, Page(s): C4
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Meet Our Editors

Editor-in-Chief
H. Joel Trussell
North Carolina State University