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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 10 • Date Oct 1988

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Displaying Results 1 - 9 of 9
  • Modular testprocessor for VLSI chips and high-density PC boards

    Publication Year: 1988, Page(s):1118 - 1124
    Cited by:  Papers (1)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB)

    A method for the test of VLSI chips and high-density PC boards is proposed. A built-in, microprogrammable test controller, called a testprocessor, applied tests to all separately testable blocks within either a VLSI chip or PC board, hence increasing controllability and observability. Facilities for test-pattern storage and test-result evaluation as well as means for test-pattern generation and re... View full abstract»

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  • Space compaction for multiple-output circuits

    Publication Year: 1988, Page(s):1105 - 1113
    Cited by:  Papers (6)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (812 KB)

    A counting signature for multiple-output circuits is introduced. It implements both time compaction and space compaction, such that a single signature is derived for all outputs, using a simple scheme with suitable built-in implementation. It is shown that there exists testability criteria that show deterministically at design time, without full-fault simulation, whether a fault is testable by the... View full abstract»

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  • An algorithm for functional reconfiguration of fixed-size arrays

    Publication Year: 1988, Page(s):1114 - 1118
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (320 KB)

    A technique for reconfiguring an array of arbitrary rectangular shape from a fixed-size square array is presented. This type of reconfiguration is referred to as functional reconfiguration, as it maps processing functionalities (given by processing) into an array of dimensions different from those of the physical device. Functional reconfiguration is analyzed using index mapping. Locality and inte... View full abstract»

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  • The generation of a mesh for resistance calculation in integrated circuits

    Publication Year: 1988, Page(s):1029 - 1037
    Cited by:  Papers (5)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (796 KB)

    A method of generating a two-dimensional irregular mesh on a resistive shape is presented. Heuristics are used to identify critical areas where small mesh elements are required. Mesh refinement is applied in these areas until elements are smaller than a specified size. In noncritical areas, elements have a natural tendency to increase in size at a restricted rate. Rapid generation of the mesh is a... View full abstract»

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  • A physical parametric transistor model for CMOS circuit simulation

    Publication Year: 1988, Page(s):1038 - 1052
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1144 KB)

    A transistor model for use in simulation of analog and digital CMOS circuits is described. This model treats inversion devices and normally off accumulation devices individually. The analysis, based on surface potential, is carried out in voltage space. Single expressions for drain current and terminal charges are obtained that conserve charge and give accurate DC, AC, and transient solutions. Der... View full abstract»

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  • Yield optimization for nondifferentiable density functions using convolution techniques

    Publication Year: 1988, Page(s):1053 - 1067
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (836 KB)

    A method of yield derivative estimation for nondifferentiable or truncated probability-density functions (PDFs) is proposed and applied to yield optimization. The method applies convolution techniques and is based on the recently introduced perturbation approach. It constructs some approximation to the original PDF and requires a small number of samples per yield-optimization-algorithm step. The m... View full abstract»

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  • Circuits for pseudoexhaustive test pattern generation

    Publication Year: 1988, Page(s):1068 - 1080
    Cited by:  Papers (32)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (956 KB)

    Implementation methods based on cyclic codes are presented for pseudoexhaustive testing of combinational logic networks with restricted output dependency. A modified linear-feedback shift register (LFSR) is used to generate exhaustive test patterns for every output of the circuit. All detectable, combinational faults (those that do not change a combinational circuit to a sequential circuit) in eac... View full abstract»

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  • Test generation for sequential circuits

    Publication Year: 1988, Page(s):1081 - 1093
    Cited by:  Papers (124)  |  Patents (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1148 KB)

    An approach to test-pattern generation for synchronous sequential circuits is presented. The deterministic sequential test-generation algorithm, based on extensions to the PODEM justification algorithm, is effective for midsized sequential circuits and can be used in conjunction with an incomplete scan design approach to generate tests for very large sequential circuits. Tests for finite-state mac... View full abstract»

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  • A new approach to three- or four-layer channel routing

    Publication Year: 1988, Page(s):1094 - 1104
    Cited by:  Papers (40)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (928 KB)

    An approach to the three-layer or four-layer channel-routing problem is presented. A general technique that transforms a two-layer routing solution systematically into a three-layer routing solution is developed. The proposed router performs well in comparison with other three-layer channel routers proposed thus far. In particular, it provides a ten-track optimal solution for the famous Deutsch's ... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu