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Electronics Packaging Manufacturing, IEEE Transactions on

Issue 1 • Date Jan. 2007

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Displaying Results 1 - 19 of 19
  • Table of contents

    Publication Year: 2007 , Page(s): C1
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  • IEEE Transactions on Electronics Packaging Manufacturing publication information

    Publication Year: 2007 , Page(s): C2
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  • Foreword Special Section on Tin Whiskers

    Publication Year: 2007 , Page(s): 1
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  • Crystallographic Texture and Whiskers in Electrodeposited Tin Films

    Publication Year: 2007 , Page(s): 2 - 10
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1699 KB) |  | HTML iconHTML  

    Electron back scatter diffraction (EBSD) analysis was used to determine texture for electrodeposited tin films, and the results were compared to standard X-ray "times random" and full pole figure texture analysis. The data showed that EBSD and X-ray texture results differed as to primary and secondary texture determinations with some degree of correlation between texture determinations when primary/secondary/tertiary calculations were disregarded. It is these authors' opinion that film texture cannot be accurately determined using "times random" X-ray diffraction (XRD) techniques, and that there is considerable room for error with X-ray pole figure analyses. These data must be considered preliminary due to the small sample size, but these results indicate that electroplaters may have better control over as-deposited tin film texture than is currently believed, and that there is a relationship between as-deposited texture and film stress View full abstract»

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  • Theory of Tin Whisker Growth: “The End Game”

    Publication Year: 2007 , Page(s): 11 - 22
    Cited by:  Papers (13)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3723 KB) |  | HTML iconHTML  

    Previous theories of the tin whisker growth proposing various dislocation mechanisms have been largely disproved. This paper presents a new and different theory for the mechanism of tin whisker growth. The theory addresses the fundamental requirements for Sn to diffuse to the base of the whisker grain and proposes a mechanism for whisker initiation and growth. Part of this is a theoretical proposal as to what makes the whisker grain different. The role of oxidation in whisker growth is also briefly addressed. Using this theory, attempts are made to illustrate how different whisker shapes are created. Finally, a proposed potential solution to tin whisker growth is presented, assuming that this theory is correct View full abstract»

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  • Sn Corrosion and Its Influence on Whisker Growth

    Publication Year: 2007 , Page(s): 23 - 35
    Cited by:  Papers (19)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6865 KB) |  | HTML iconHTML  

    The microstructure and crystal structure of condensation-induced corrosion products, vapor phase induced oxidation products, Cu-Sn intermetallics, and Sn whiskers that formed on electroplated matte Sn on Cu-alloy after exposure 2500 h in a 60 degC/93%RH ambient were characterized with scanning electron microscopy, (SEM), focused ion beam (FIB) microscopy, energy dispersive spectroscopy (EDS), transmission electron microscopy (TEM), and selected area electron diffraction (SAD). The corrosion product was identified as crystalline SnO2. The oxidation of Sn in condensed water was at least four orders of magnitude larger than that in moist vapor at 60 degC. All Sn whiskers were found to be within 125 mum of the corrosion product. Based on these observations, a theory was developed. The theory assumes that oxidation leads to the displacement of Sn atoms within the film. Because the grain boundaries and free surfaces of the film are pinned, the oxidation-induced excess Sn atoms are constrained within the original volume of the Sn-film. The trapped excess Sn atoms create localized stress, excess strain energy, in the Sn-film. If and when the pinning constraint is relaxed, as for example would occur when the surface oxide on the film cracks, then the Sn atoms can diffuse to lower energy configurations. When this occurs, whisker nucleation and growth begins. The theory was tested by detailed measurements and comparison of the corrosion volume and the whisker volume in two different samples. The volume comparisons were consistent with the theory View full abstract»

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  • Length Distribution Analysis for Tin Whisker Growth

    Publication Year: 2007 , Page(s): 36 - 40
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1256 KB) |  | HTML iconHTML  

    The global movement to lead-free electronics has led semiconductor device assemblers to switch terminals and finishes from lead-based to pure tin or high tin lead-free alloys. This transition has resulted in a reliability concern associated with the formation of conductive tin whiskers, which can grow from a device terminal or lead and cause current leakage or short circuits. This paper presents the results of an experimental study on tin whisker growth. Test specimens consisted of matte and bright tin finishes on copper, Alloy-42, and brass substrate materials. The heat treatments included annealing and two types of simulated reflow. Maximum whisker length and whisker density were measured on 24 different types of tin-plated specimens, after three, eight, and 16 months of room ambient storage after various heat treatments View full abstract»

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  • Foreword Special Section on Drop Testing

    Publication Year: 2007 , Page(s): 41
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  • A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages

    Publication Year: 2007 , Page(s): 42 - 48
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1519 KB) |  | HTML iconHTML  

    As handheld electronic products are more prone to being dropped during useful life, package-to-board interconnect reliability has become a major concern for these products. This has prompted the industry to evaluate the drop performance of chip-scale packages (CSPs) while mounted on printed wiring boards using board-level drop testing. Although a new board-level test method has been standardized through JEDEC (JESD22-B111), characterization tests take quite a long time to complete, extending the design cycle. This paper proposes a method to compare and evaluate the drop performance through simulations at the design stage. A global-local approach is used to first determine the dynamic response of the board during drop and then to translate it into stresses and strain energy density in solder joints and intermetallic layers. The dynamic response of the board is validated by using data from actual board level testing as per JEDEC standard. The solder joint and intermetallic stresses are then related to drop to failure test data to derive a relative prediction model. The method is then applied to quantify the effect of package design parameters on the drop performance. Factors considered include moldcap thickness, ball pad opening, and land grid array (LGA) versus ball grid array (BGA). The same factors were tested in board level drop to further validate the prediction model. The results indicate that the drop performance can be increased by a factor of 2 or more by changing package design variables View full abstract»

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  • Failure Morphology After Drop Impact Test of Ball Grid Array (BGA) Package With Lead-Free Sn–3.8Ag–0.7Cu and Eutectic SnPb Solders

    Publication Year: 2007 , Page(s): 49 - 53
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (3732 KB) |  | HTML iconHTML  

    High strain-rate drop impact tests were performed on ball grid array (BGA) packages with solder compositions of (in wt%) Sn-3.8Ag-0.7Cu (SnAgCu) and eutectic Sn-37Pb (SnPb). Solder balls were joined to the metallizations of plated Ni on the device side and plated Cu on the board side. The BGA packages were tested at 1500 g within 0.5 ms, resulting in an imposed bending strain of 0.2-0.3%. Both SnAgCu and SnPb joints failed at the interface at the device side but the detailed failure morphology differed significantly. The crack location for the eutectic SnPb was primarily through the solder and seldom extended through an entire bump. The SnPb joints also exhibited bulk solder deformation. The SnAgCu joints showed extremely brittle behavior with an interfacial failure at the (Ni,Cu)3Sn4 intermetallics/Ni under bump metallization (UBM) interface. The strain rate sensitivity of bulk solder defines the drop test performance and the eutectic SnPb solder showed better drop impact performance due to a less strain rate sensitivity View full abstract»

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  • Transient Submodeling Analysis for Board-Level Drop Tests of Electronic Packages

    Publication Year: 2007 , Page(s): 54 - 62
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2492 KB) |  | HTML iconHTML  

    We present in this paper a submodeling analysis procedure capable of solving transient mechanical responses of board-level electronic packages subjected to drop impact loads, involving large deformations and nonlinear elastoplastic constitutive relationships for the solder alloy. This paper is focused on the verification of this submodeling analysis procedure and to investigate solution deviations caused by several abbreviated global models that involve simplified geometry or material properties for the solder joints View full abstract»

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  • Investigation of the Role of Void Formation at the Cu-to-Intermetallic Interface on Aged Drop Test Performance

    Publication Year: 2007 , Page(s): 63 - 73
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (8276 KB) |  | HTML iconHTML  

    Chip-scale packages (CSPs) are widely used in portable electronic products. Mechanical drop testing is a critical reliability requirement for these products. With the switch to lead-free solder, new reliability data must be generated. Most drop test reliability data reported for CSPs are for the as-built condition. However, the mechanical shock reliability over the life of the product is equally important. This paper provides a systematic study of surface finish (immersion Sn and immersion Ag) and reflow profile (cool down rate) on the drop test reliability of CSP assemblies. A limited experiment was also performed with organic solderability preservative (OSP)-coated boards. The Sn finish provides an initial Cu-Sn intermetallic layer, while the Ag finish and OSP coating allows the formation of the initial Cu-Sn intermetallic during the reflow cycle. Drop test results for assemblies as-built and as a function of aging at 125 degC are correlated with cross-sectional analysis of the solder joints. The mean number of drops to failure decreases by approximately 80% with aging at 125 degC through 480 h. Voids develop at the Cu-Sn intermetallic-to-Cu interface during high-temperature aging, but the crack path is through the intermetallic layer and does not propagate from void-to-void. Thus, it can be concluded that the voids do not contribute to the decrease in drop test survivability observed in this study View full abstract»

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  • Solder Joint Reliability in Electronics Under Shock and Vibration Using Explicit Finite-Element Submodeling

    Publication Year: 2007 , Page(s): 74 - 83
    Cited by:  Papers (44)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1982 KB) |  | HTML iconHTML  

    Modeling approaches for first-level solder interconnects in shock and drop of electronics assemblies have been developed without any assumptions of geometric symmetry or loading symmetry. The problem involves multiple scales from macroscale transient-dynamics of electronic assembly to microstructural damage history of interconnects. Previous modeling approaches include, solid-to-solid submodeling using a half test PCB board, shell-to-solid submodeling technique using a quarter-symmetry model. Inclusion of model symmetry in state-of-the-art models saves computational time but targets primarily symmetric mode shapes. The modeling approach proposed in this paper enables prediction of both symmetric and antisymmetric modes, which may dominate an actual drop-event. Approaches investigated include smeared property models, Timoshenko-beam element models, explicit submodels, and continuum-shell models. Transient dynamic behavior of the board assemblies in free and JEDEC drop has been measured using high-speed strain and displacement measurements. Model predictions have been correlated with experimental data View full abstract»

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  • Insights Into Correlation Between Board-Level Drop Reliability and Package-Level Ball Impact Test Characteristics

    Publication Year: 2007 , Page(s): 84 - 91
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1785 KB) |  | HTML iconHTML  

    The ball impact test (BIT) is developed based on the demand of a package-level measure for the board-level drop reliability of solder joints in the sense that it leads to fracturing of solder joints around the intermetallics, similar to that from a board-level drop test. In this paper, both board-level drop test and package-level ball impact test are examined numerically for solder joints of different Sn-Ag-Cu compositions. We propose a stress-based drop reliability index that involves the strength of intermetallics and the maximum interfacial normal stress the solder joints have experienced during the drop impact process. Correlations between the drop reliability index and BIT characteristics are found to be dependent on solder compositions. However, the correlations appear to be universal, i.e., independent of solder compositions, when certain constant multipliers are introduced View full abstract»

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  • Leading the field since 1884 [advertisement]

    Publication Year: 2007 , Page(s): 92
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  • IEEE Transactions on Advanced Packaging - Table of contents

    Publication Year: 2007 , Page(s): 93 - 94
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  • Table of contents

    Publication Year: 2007 , Page(s): 95 - 96
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  • IEEE Components, Packaging, and Manufacturing Technology Society Information for authors

    Publication Year: 2007 , Page(s): C3
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  • IEEE Components, Packaging, and Manufacturing Technology Society Information

    Publication Year: 2007 , Page(s): C4
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Aims & Scope

IEEE Transactions on Electronics Packaging Manufacturing addresses design for manufacturability, cost and process modeling, process control and automation, factory analysis and improvement, information systems, statistical methods, environmentally friendly processing, and computer-integrated manufacturing for the production of electronic assemblies and products.

 

This Transaction ceased production in 2010. The current publication is titled IEEE Transactions on Components, Packaging, and Manufacturing Technology.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
R. Wayne Johnson
Auburn University