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Computers & Digital Techniques, IET

Issue 1 • Date January 2007

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Displaying Results 1 - 6 of 6
  • System-on-chip communication architecture: dynamic parallel fraction control bus design and test methodologies

    Publication Year: 2007 , Page(s): 1 - 8
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (344 KB)  

    Modern system-on-chip (SOC) designs consist of numerous heterogeneous components (embedded CPUs, dedicated hardware, FPGAs, embedded memories and so on) integrated onto a single chip. The on-chip communication is becoming the bottleneck for these SOC designs, and efficient contention resolution schemes for managing simultaneous access requests to the communication resources are required to prevent... View full abstract»

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  • Optimised realisations of large integer multipliers and squarers using embedded block

    Publication Year: 2007 , Page(s): 9 - 16
    Cited by:  Papers (5)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (634 KB)  

    An efficient design methodology and a systematic approach for the implementation of multiplication and squaring functions for unsigned large integers, using small-size embedded multipliers are presented. A general architecture of the multiplier and squarer is proposed and a set of equations is derived to aid in the realisation. The inputs of the multiplier and squarer are split into several segmen... View full abstract»

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  • ROM to DSP block transfer for resource constrained synthesis

    Publication Year: 2007 , Page(s): 17 - 26
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (308 KB)  

    Modern field programmable gate array (FPGA) architectures are moving towards heterogeneity with the increasing inclusion of coarse grained elements such as embedded multipliers and RAMs. This has given rise to a multi-dimensioned resource-based measure of design area, very different from the traditional application-specific integrated circuit figure of silicon area. In order for a designer to use ... View full abstract»

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  • Test data truncation for test quality maximisation under ATE memory depth constraint

    Publication Year: 2007 , Page(s): 27 - 37
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (622 KB)  

    Testing is used to ensure production of high quality integrated circuits. High test quality implies the application of high quality test data; however, technology development has led to a need to increase test data volumes to ensure high test quality. The problem is that the high test data volume leads to long test application times and high automatic test equipment memory requirement. For a modul... View full abstract»

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  • RNS multiplication/sum-of-squares units

    Publication Year: 2007 , Page(s): 38 - 48
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (496 KB)  

    Digital signal processing and multimedia applications often profit from the use of a residue number system. Among the most commonly used moduli, in such systems, are those of 2n-1 and 2n+1 forms and among the most commonly used operations are multiplication and sum-of-squares. These operations are currently performed using distinct design units and/or consecutive machine cycl... View full abstract»

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  • Design of efficient modulo 2n + 1 multipliers

    Publication Year: 2007 , Page(s): 49 - 57
    Cited by:  Papers (23)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (333 KB)  

    A new modulo 2n+1 multiplier architecture is proposed for operands in the weighted representation. A new set of partial products is derived and it is shown that all required correction factors can be merged into a single constant one. It is also proposed that part of the correction factor is treated as a partial product, whereas the rest is handled by the final parallel adder. The propo... View full abstract»

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Aims & Scope

IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems.

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