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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 9 • Date Sep 1988

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Displaying Results 1 - 9 of 9
  • Improved net merging method for gate matrix layout

    Publication Year: 1988 , Page(s): 947 - 951
    Cited by:  Papers (5)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (364 KB)  

    A net-merging method is proposed for gate-matrix layout. The method is based on a density function to calculate the minimum number of tracks necessary for the net assignment. Examples that demonstrate how this method leads to a denser gate matrix layout are included. The pitch of the gate columns is determined by the design rules, in particular, the space required to accommodate a diffused region ... View full abstract»

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  • A new aggregation technique for the solution of large systems of algebraic equations [IC simulation]

    Publication Year: 1988 , Page(s): 976 - 986
    Cited by:  Papers (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (728 KB)  

    The term aggregation denotes a class of methods that were originally conceived as a way to compute an approximate solution of a linear system of equations. It has been shown that they could be used to accelerate the convergence of linear relaxation algorithms. Although all aggregation methods rely on the same general idea, each individual method is usually based on a heuristic that is valid for a ... View full abstract»

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  • Device and circuit simulation interface for an integrated VLSI design environment

    Publication Year: 1988 , Page(s): 998 - 1004
    Cited by:  Papers (3)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (552 KB)  

    MOSGEN, a program that provides efficient interface between the device simulator, PISCES and the circuit simulator SPICE, is described. Algorithms to generate parameters for SPICE built-in MOS transistor models have been developed and incorporated into MOSGEN. Only six PISCES simulation results are required to generate a complete set of SPICE parameters. This interface program, together with SUPRE... View full abstract»

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  • A compact IGFET model-ASIM

    Publication Year: 1988 , Page(s): 952 - 975
    Cited by:  Papers (22)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1416 KB)  

    A description is given of ASIM (AT&T short-channel IGFET model), a circuit-level model for enhancement-type MOSFETs. A detailed description of the model formulation is presented and the assumptions used in the derivation of model equations are stated. ASIM is generally applicable to MOS transistors with small physical dimensions, ion-implanted substrates, and lightly doped source and drain reg... View full abstract»

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  • Switch-level simulation and the pass transistor EXOR gate

    Publication Year: 1988 , Page(s): 994 - 997
    Cited by:  Papers (6)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (288 KB)  

    The nonrestoring pass transistor EXOR gate is investigated by switch-level simulation. It is shown that the logical function of the EXOR gate depends on the driving conductance on the inputs to the gate. It is also shown why switch-level simulators are unsuccessful in simulating the pass transistor EXOR gate, and how a switch-level simulator can be designed to produce a correct simulation result View full abstract»

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  • PISCES-MC: a multiwindow, multimethod 2-D device simulator

    Publication Year: 1988 , Page(s): 1017 - 1026
    Cited by:  Papers (10)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (860 KB)  

    A multiwindow, multimethod device analysis algorithm that combines the advantages of efficient drift-diffusion simulators and accurate physical models using Monte Carlo methods is described. The PISCES 2-D device analysis program is used whenever the drift-diffusion model is valid. In situations where the drift-diffusion model breaks down, a window is opened in the part of the device where the hot... View full abstract»

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  • Detectability of CMOS stuck-open faults using random and pseudorandom test sequences

    Publication Year: 1988 , Page(s): 933 - 946
    Cited by:  Papers (6)  |  Patents (1)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (848 KB)  

    An analysis is presented of CMOS stuck-open faults tested with a pseudorandom test sequence, i.e. a test sequence consisting of some or all of the 2N test patterns generated by a modified N-bit linear-feedback shift register (LFSR). Such a scheme is viewed as testing without replacement. When all 2N test patterns are applied, then such a test sequence is called a pse... View full abstract»

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  • Simulating digital circuits with one bit per wire

    Publication Year: 1988 , Page(s): 987 - 993
    Cited by:  Papers (14)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (616 KB)  

    An algorithm to simulate synchronous digital logic circuits in space proportional to one bit per wire, as long as the specification has a hierarchical nature, is described. An entire simulation might fit in the fast cache of some computers. The simulation algorithm is simple to implement, and runs relatively quickly. Although the algorithm has a quadratic worst-case running time, empirical results... View full abstract»

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  • MOZART: a concurrent multilevel simulator

    Publication Year: 1988 , Page(s): 1005 - 1016
    Cited by:  Papers (34)  |  Patents (2)
    Request Permissions | Click to expandAbstract | PDF file iconPDF (1080 KB)  

    MOZART, a concurrent fault simulator for large circuits described at the register-transfer, functional, gate, and switch levels, is described. The requirements of multilevel simulation have guided the definition of MOZART's syntax, value set, delay model, and algorithms. Performance is improved by reducing unnecessary activity. Two such techniques are levelized: two-pass simulation, which minimize... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu