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Computers, IEEE Transactions on

Issue 3 • Date March 2007

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Displaying Results 1 - 16 of 16
  • [Front cover]

    Page(s): c1
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  • [Inside front cover]

    Page(s): c2
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  • Lightweight Error Correction Coding for System-Level Interconnects

    Page(s): 289 - 304
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7066 KB) |  | HTML iconHTML  

    "Lightweight hierarchical error control coding (LHECC)" is a new class of nonlinear block codes that is designed to increase noise immunity and decrease error rate for high-performance chip-to-chip and on-chip interconnects. LHECC is designed such that its corresponding encoder and decoder logic may be tightly integrated into compact, high-speed, and low-latency I/O interfaces. LHECC operates over a new channel technology called multi-bit differential signaling (MBDS). MBDS channels utilize a physical-layer channel code called "N choose M (nCm)" encoding, where each channel is restricted to a symbol set such that half of the bits in each symbol are set to one. These symbol sets have properties that are utilized by LHECC to achieve error correction capability while requiring low or zero relative information overhead. In addition, these codes may be designed such that the latency and size of the corresponding decoders are tightly bounded. The effectiveness of these codes is demonstrated by modeling error behavior of MBDS interconnects over a range of transmission rates and noise characteristics View full abstract»

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  • Double Point Compression with Applications to Speeding Up Random Point Multiplication

    Page(s): 305 - 313
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1336 KB) |  | HTML iconHTML  

    This paper presents two main results relating to elliptic curve cryptography. First, a double point compression scheme is proposed which allows a compact representation of elliptic curve points without the computational cost associated with ordinary single point compression. A triple point compression scheme is also proposed which can result in more savings in memory and/or bandwidth. Second, a new approach to speeding up random point multiplication is given for the case where the base point is variable but available in a certificate. In this approach, some redundant information (a few multiples of the base point) is added to the certificate. It is shown that a significant speed up can be obtained by optimizing the Moller's algorithm for the case where only a portion of the lookup table is available. It is also shown how to use redundant information to compute random point multiplication using parallel processors. The proposed point compression schemes can be employed to reduce the required bandwidth when single point compression is computationally expensive View full abstract»

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  • $log_{rm n}{rm P}$ and $log_{3}{rm P}$: Accurate Analytical Models of Point-to-Point Communication in Distributed Systems

    Page(s): 314 - 327
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2781 KB) |  | HTML iconHTML  

    Many existing models of point-to-point communication in distributed systems ignore the impact of memory and middleware. Including such details may make these models impractical. Nonetheless, the growing gap between memory and CPU performance combined with the trend toward large-scale, clustered shared memory platforms implies an increased need to consider the impact of middleware on distributed communication. We present a general software-parameterized model of point-to-point communication for use in performance prediction and evaluation. We illustrate the utility of the model in three ways: 1) to derive a simplified, useful, more accurate model of point-to-point communication in clusters of SMPs, 2) to predict and analyze point-to-point and broadcast communication costs in clusters of SMPs, and 3) to express, compare, and contrast existing communication models. Though our methods are general, we present results on several Linux clusters to illustrate practical use on real systems View full abstract»

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  • Miss Rate Prediction Across Program Inputs and Cache Configurations

    Page(s): 328 - 343
    Multimedia
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (7174 KB) |  | HTML iconHTML  

    Improving cache performance requires understanding cache behavior. However, measuring cache performance for one or two data input sets provides little insight into how cache behavior varies across all data input sets and all cache configurations. This paper uses locality analysis to generate a parameterized model of program cache behavior. Given a cache size and associativity, this model predicts the miss rate for arbitrary data input set sizes. This model also identifies critical data input sizes where cache behavior exhibits marked changes. Experiments show this technique is within 2 percent of the hit rate for set associative caches on a set of floating-point and integer programs using array and pointer-based data structures. Building on the new model, this paper presents an interactive visualization tool that uses a three-dimensional plot to show miss rate changes across program data sizes and cache sizes and its use in evaluating compiler transformations. Other uses of this visualization tool include assisting machine and benchmark-set design. The tool can be accessed on the Web at http://www.cs.rochester.edu/research/locality View full abstract»

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  • Adaptive Resource Allocation Control for Fair QoS Management

    Page(s): 344 - 357
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1993 KB) |  | HTML iconHTML  

    A novel control method for fair resource allocation and maximization of the quality of service (QoS) levels of individual tasks is proposed. In the proposed adaptive QoS controller, resource utilization is assigned to each task through an online search for the fair QoS level based on the errors between the current QoS levels and their average. The proposed controller eliminates the need for precise detection of the consumption functions as in conventional feedback control methods. The computational complexity of the proposed method is also very low compared to straightforward methods solving a nonlinear problem View full abstract»

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  • Energy-Aware Modeling and Scheduling for Dynamic Voltage Scaling with Statistical Real-Time Guarantee

    Page(s): 358 - 372
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1456 KB) |  | HTML iconHTML  

    Dynamic voltage scaling (DVS) is a promising technique for battery-powered systems to conserve energy consumption. Most existing DVS algorithms assume information about task periodicity or a priori knowledge about the task set to be scheduled. This paper presents an analytical model of general tasks for DVS assuming job timing information is known only after a task release. It models the voltage scaling process as a transfer function-based filtering system, which facilitates the design of two efficient scaling algorithms. The first is a time-invariant scaling policy and it is proved to be a generalization of several popular DVS algorithms for periodic, sporadic, and aperiodic tasks. A more energy efficient policy is a time-variant scaling algorithm for aperiodic tasks. It is optimal in the sense that it is online without assumed information about future task releases. The algorithm turns out to be a water-filling process with a linear time complexity. It can be applied to scheduling based on worst-case execution times as well as online slack distribution when jobs complete earlier. We further establish two relationships between computation capacity and deadline misses to provide a statistical real-time guarantee with reduced capacity View full abstract»

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  • Space-Optimal, Wait-Free Real-Time Synchronization

    Page(s): 373 - 384
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2940 KB) |  | HTML iconHTML  

    We consider wait-free synchronization for the single-writer/multiple-reader problem in small-memory embedded real-time systems. We present an analytical solution to the problem of determining the minimum, optimal space cost required for this problem, considering a priori knowledge of interferences $the first such result. We also show that the space costs required by previous algorithms can be obtained by our analytical solution, which subsumes them as special cases. We also present a wait-free protocol that utilizes the minimum space cost determined by our analytical solution. Our evaluation studies and implementation measurements using the SHaRK RTOS kernel validate our analytical results View full abstract»

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  • Utility Accrual Real-Time Scheduling under Variable Cost Functions

    Page(s): 385 - 401
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2878 KB) |  | HTML iconHTML  

    We present a utility accrual real-time scheduling algorithm called CIC-VCUA for tasks whose execution times are functions of their starting times (and, potentially, other factors). We model such variable execution times using variable cost functions (or VCFs). The algorithm considers application activities that are subject to time/utility function time constraints, execution times described using VCFs, and mutual exclusion constraints on concurrent sharing of non-CPU resources. We consider the twofold scheduling objective of 1) assuring that the maximum interval between any two consecutive, successful completions of job instances in an activity must not exceed the activity period (an application-specific objective) and 2) maximizing the system's total accrued utility while satisfying mutual exclusion resource constraints. Since the scheduling problem is intractable, CIC-VCUA is a polynomial-time heuristic algorithm. The algorithm statically computes worst-case task sojourn times, dynamically selects tasks for execution based on their potential utility density, and completes tasks at specific times. We establish that CIC-VCUA achieves optimal timeliness during underloads, and tightly upper bounds inter and intratask completion times. Our simulation experiments confirm the algorithm's effectiveness and superiority View full abstract»

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  • Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis

    Page(s): 402 - 414
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (4048 KB) |  | HTML iconHTML  

    Column selection row parity (CPRS) diagnosis is an X-tolerant and low aliasing technique that is suitable for the BIST environment. A row selection LFSR randomly selects outputs of multiple scan chains so that unknowns can be tolerated. Column and row parities of selected outputs are observed to solve linear equations for the error positions. Experimental data show that CPRS achieves nearly perfect diagnosis, even in the presence of 1 percent unknowns. CPRS compresses the diagnosis data because only parities of circuit responses, instead of responses themselves, are observed. Two error distribution models (scattered and clustered) are developed and analyzed to show the effectiveness of CPRS. The analytical results are demonstrated to be accurate by more than 10,000 experiments View full abstract»

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  • Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?

    Page(s): 415 - 428
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2374 KB) |  | HTML iconHTML  

    In today's high performance (multi-GHz) microprocessors' design, on-chip clock calibration features are needed to compensate for electrical parameter variations as a result of manufacturing process variations. The calibration features allow performance boost after manufacturing test and maintain such performance levels during normal operation, thus preserving product quality. This strategy has been proven successful commercially. In this paper, we discuss the impact on performance and product quality of both permanent and transient faults possibly affecting these calibration circuits during manufacturing and normal operation, respectively. In particular, we consider the case of an on-chip clock calibration feature of a commercial high performance microprocessor. We show that some possible permanent faults may render the on-chip clock calibration schemes useless (in process variations' compensation), while it is impossible for common manufacturing testing to detect this incorrect behavior. This means that a faulty operating microprocessor may pass the testing phase and be put onto the market, with a consequent impact on product quality and increase in defect level. Similarly, we show that some possible transient faults occurring during the microprocessor in-field operation could defeat the purpose of on-chip clock calibration, again resulting in faulty operation of the microprocessor. This has long range implications to microprocessors' design as well, considering that process variations on die, as well as across the process, would worsen with continued scaling. Proper strategies to test these clock calibration features and to guarantee their correct operation in the field cannot be ignored. Possible design approaches to solve this problem are discussed View full abstract»

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  • An Upper Bound for the Bisection Width of a Diagonal Mesh

    Page(s): 429 - 431
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (792 KB) |  | HTML iconHTML  

    Recently, it was correctly pointed out by Jha that there is an error in our earlier paper on diagonal mesh networks. In response to Jha's critique, we now provide an upper bound on the bisection width of a diagonal mesh. The proof is a constructive one and an algorithm is provided to divide the network into two equal halves (plus/minus one node) View full abstract»

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  • In this issue

    Page(s): 432
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  • TC Information for authors

    Page(s): c3
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  • [Back cover]

    Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Albert Y. Zomaya
School of Information Technologies
Building J12
The University of Sydney
Sydney, NSW 2006, Australia
http://www.cs.usyd.edu.au/~zomaya
albert.zomaya@sydney.edu.au