# IEEE Transactions on Computers

## Filter Results

Displaying Results 1 - 16 of 16
• ### [Front cover]

Publication Year: 2007, Page(s): c1
| PDF (99 KB)
• ### [Inside front cover]

Publication Year: 2007, Page(s): c2
| PDF (82 KB)
• ### Lightweight Error Correction Coding for System-Level Interconnects

Publication Year: 2007, Page(s):289 - 304
Cited by:  Papers (1)  |  Patents (10)
| | PDF (7066 KB) | HTML

"Lightweight hierarchical error control coding (LHECC)" is a new class of nonlinear block codes that is designed to increase noise immunity and decrease error rate for high-performance chip-to-chip and on-chip interconnects. LHECC is designed such that its corresponding encoder and decoder logic may be tightly integrated into compact, high-speed, and low-latency I/O interfaces. LHECC operates over... View full abstract»

• ### Double Point Compression with Applications to Speeding Up Random Point Multiplication

Publication Year: 2007, Page(s):305 - 313
Cited by:  Papers (6)  |  Patents (1)
| | PDF (1336 KB) | HTML

This paper presents two main results relating to elliptic curve cryptography. First, a double point compression scheme is proposed which allows a compact representation of elliptic curve points without the computational cost associated with ordinary single point compression. A triple point compression scheme is also proposed which can result in more savings in memory and/or bandwidth. Second, a ne... View full abstract»

• ### $log_{rm n}{rm P}$ and $log_{3}{rm P}$: Accurate Analytical Models of Point-to-Point Communication in Distributed Systems

Publication Year: 2007, Page(s):314 - 327
Cited by:  Papers (16)
| | PDF (2781 KB) | HTML

Many existing models of point-to-point communication in distributed systems ignore the impact of memory and middleware. Including such details may make these models impractical. Nonetheless, the growing gap between memory and CPU performance combined with the trend toward large-scale, clustered shared memory platforms implies an increased need to consider the impact of middleware on distributed co... View full abstract»

• ### Miss Rate Prediction Across Program Inputs and Cache Configurations

Publication Year: 2007, Page(s):328 - 343
Cited by:  Papers (15)
| | PDF (7174 KB) | HTML Media

Improving cache performance requires understanding cache behavior. However, measuring cache performance for one or two data input sets provides little insight into how cache behavior varies across all data input sets and all cache configurations. This paper uses locality analysis to generate a parameterized model of program cache behavior. Given a cache size and associativity, this model predicts ... View full abstract»

• ### Adaptive Resource Allocation Control for Fair QoS Management

Publication Year: 2007, Page(s):344 - 357
Cited by:  Papers (26)
| | PDF (1993 KB) | HTML

A novel control method for fair resource allocation and maximization of the quality of service (QoS) levels of individual tasks is proposed. In the proposed adaptive QoS controller, resource utilization is assigned to each task through an online search for the fair QoS level based on the errors between the current QoS levels and their average. The proposed controller eliminates the need for precis... View full abstract»

• ### Energy-Aware Modeling and Scheduling for Dynamic Voltage Scaling with Statistical Real-Time Guarantee

Publication Year: 2007, Page(s):358 - 372
Cited by:  Papers (63)
| | PDF (1456 KB) | HTML

Dynamic voltage scaling (DVS) is a promising technique for battery-powered systems to conserve energy consumption. Most existing DVS algorithms assume information about task periodicity or a priori knowledge about the task set to be scheduled. This paper presents an analytical model of general tasks for DVS assuming job timing information is known only after a task release. It models the voltage s... View full abstract»

• ### Space-Optimal, Wait-Free Real-Time Synchronization

Publication Year: 2007, Page(s):373 - 384
Cited by:  Papers (7)
| | PDF (2940 KB) | HTML

We consider wait-free synchronization for the single-writer/multiple-reader problem in small-memory embedded real-time systems. We present an analytical solution to the problem of determining the minimum, optimal space cost required for this problem, considering a priori knowledge of interferences \$the first such result. We also show that the space costs required by previous algorithms can be obta... View full abstract»

• ### Utility Accrual Real-Time Scheduling under Variable Cost Functions

Publication Year: 2007, Page(s):385 - 401
Cited by:  Papers (7)  |  Patents (1)
| | PDF (2878 KB) | HTML

We present a utility accrual real-time scheduling algorithm called CIC-VCUA for tasks whose execution times are functions of their starting times (and, potentially, other factors). We model such variable execution times using variable cost functions (or VCFs). The algorithm considers application activities that are subject to time/utility function time constraints, execution times described using ... View full abstract»

• ### Column Parity Row Selection (CPRS) BIST Diagnosis Technique: Modeling and Analysis

Publication Year: 2007, Page(s):402 - 414
Cited by:  Papers (5)
| | PDF (4048 KB) | HTML

Column selection row parity (CPRS) diagnosis is an X-tolerant and low aliasing technique that is suitable for the BIST environment. A row selection LFSR randomly selects outputs of multiple scan chains so that unknowns can be tolerated. Column and row parities of selected outputs are observed to solve linear equations for the error positions. Experimental data show that CPRS achieves nearly perfec... View full abstract»

• ### Won't On-Chip Clock Calibration Guarantee Performance Boost and Product Quality?

Publication Year: 2007, Page(s):415 - 428
Cited by:  Papers (11)
| | PDF (2374 KB) | HTML

In today's high performance (multi-GHz) microprocessors' design, on-chip clock calibration features are needed to compensate for electrical parameter variations as a result of manufacturing process variations. The calibration features allow performance boost after manufacturing test and maintain such performance levels during normal operation, thus preserving product quality. This strategy has bee... View full abstract»

• ### An Upper Bound for the Bisection Width of a Diagonal Mesh

Publication Year: 2007, Page(s):429 - 431
Cited by:  Papers (2)
| | PDF (792 KB) | HTML

Recently, it was correctly pointed out by Jha that there is an error in our earlier paper on diagonal mesh networks. In response to Jha's critique, we now provide an upper bound on the bisection width of a diagonal mesh. The proof is a constructive one and an algorithm is provided to divide the network into two equal halves (plus/minus one node) View full abstract»

• ### In this issue

Publication Year: 2007, Page(s): 432
| PDF (25 KB)
• ### TC Information for authors

Publication Year: 2007, Page(s): c3
| PDF (82 KB)
• ### [Back cover]

Publication Year: 2007, Page(s): c4
| PDF (99 KB)

## Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24
10129 Torino - Italy
e-mail: pmo@computer.org