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IEEE Design & Test of Computers

Issue 5 • Oct. 1987

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Displaying Results 1 - 24 of 24
  • IEEE Design & Test of Computers

    Publication Year: 1987, Page(s): c1
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  • Tables of contents

    Publication Year: 1987, Page(s):c2 - 1
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  • Editorial board

    Publication Year: 1987, Page(s): 2
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  • IEEE International Conference on Computer Design: VLSI in Computers & Processors

    Publication Year: 1987, Page(s):3 - 10
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  • First Call for Papers

    Publication Year: 1987, Page(s): 11
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  • Industry Briefs

    Publication Year: 1987, Page(s):12 - 18
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  • Parallel Processing for CAD Applications

    Publication Year: 1987, Page(s):13 - 17
    Cited by:  Papers (3)  |  Patents (2)
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  • Multipurpose Parallelism for VLSI Cad on the RP3

    Publication Year: 1987, Page(s):19 - 27
    Cited by:  Papers (7)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5361 KB)

    VLSI CAD application developers need the performance of parallel processing in as general a form as possible. The RP3, which is being developed at IBM's Research Division, provides such generality. Several CAD applications are among the more than 30 applications that have been written in the Epex parallel environment for porting to RP3 when the hardware is complete. Placement by simulated annealin... View full abstract»

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  • Enter the Annual Gordon Bell Awards for Parallel Processing Speedup

    Publication Year: 1987, Page(s): 27
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  • MARS: A Multiprocessor-Based Programmable Accelerator

    Publication Year: 1987, Page(s):28 - 36
    Cited by:  Papers (32)  |  Patents (24)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8032 KB)

    MARS, short for microprogrammable accelerator for rapid simulations, is a multiprocessor-based hardware accelerator that can efficiently implement a wide range of computationally complex algorithms. In addition to accelerating many graph-related problem solutions, MARS is ideally suited for performing event-driven simulations of VLSI circuits. Its highly pipelined and parallel architecture yields ... View full abstract»

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  • D&T Calendar

    Publication Year: 1987, Page(s): 37
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  • An Isma Lee Router Accelerator

    Publication Year: 1987, Page(s):38 - 45
    Cited by:  Papers (7)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7468 KB)

    By concentrating on application-specific behavior, extremely simple and fast state machines can be designed and replicated into arrays that fit in one or two chips. Called an iterative state machine array, this architecture can increase speed by a factor of 1000 over the speed possible with traditional software design automation tools. Because the basic ISMA cells are so simple, designers can use ... View full abstract»

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  • D&T Roundtable

    Publication Year: 1987, Page(s):46 - 51
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  • D&T Scene

    Publication Year: 1987, Page(s):52 - 53
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  • Erratum

    Publication Year: 1987, Page(s): 52
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  • Design Automation Technical Committee Newsletter

    Publication Year: 1987, Page(s):54 - 55
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  • New Products Design

    Publication Year: 1987, Page(s):56 - 57
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  • New Products Test

    Publication Year: 1987, Page(s):58 - 60
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  • D&T Conferences

    Publication Year: 1987, Page(s):61 - 63
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  • Attention Readers! Save the Reputation of Your Colleagues!

    Publication Year: 1987, Page(s): 63
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  • Advertiser/Product Index

    Publication Year: 1987, Page(s): 64
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  • IEEE Design & Test of Computers

    Publication Year: 1987, Page(s):64-a - 64-b
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  • The Computer Society

    Publication Year: 1987, Page(s): 64-c
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  • Teaching Network Design [advertisement]

    Publication Year: 1987, Page(s): 64d
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty