IEEE Design & Test of Computers

Issue 4 • Aug. 1987

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Displaying Results 1 - 25 of 26
  • IEEE Design & Test of Computers

    Publication Year: 1987, Page(s): c1
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  • Real-Time' Solution to ASIC Verification [advertisement]

    Publication Year: 1987, Page(s): c2
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  • Editorial Board

    Publication Year: 1987, Page(s): 1
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  • Tables of contents

    Publication Year: 1987, Page(s):2 - 3
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  • International Test Conference 1987

    Publication Year: 1987, Page(s):4 - 14
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  • Switch-Level Techniques

    Publication Year: 1987, Page(s):15 - 16
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  • New for Network Designers [advertisement]

    Publication Year: 1987, Page(s): 17
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  • An Introduction to Switch-Level Modeling

    Publication Year: 1987, Page(s):18 - 25
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6523 KB)

    Switch-level modeling is a recently developed design and analysis methodology for MOS VLSI circuits. At the switch level, important features of MOS circuits can be directly modeled using a moderate number of discrete parameters, including switch states, resistance, capacitance, and bidirectional signals. Switch-level models, provide more accurate behavioral and structural information than gate-lev... View full abstract»

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  • A Survey of Switch-Level Algorithms

    Publication Year: 1987, Page(s):26 - 40
    Cited by:  Papers (41)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (14766 KB)

    The switch-level model provides a logical abstraction from the physical structure of a metal-oxide semiconductor(MOS) circuit to its digital behavior. At the switch level, a circuit is modeled as a network of transistor switches connecting a set of charge storage nodes. Node voltages are represented by discrete logic levels, and electrical behavior is modeled in a highly simplified way. Switch-lev... View full abstract»

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  • ITC. The Only Serious Place for Test [advertisement]

    Publication Year: 1987, Page(s): 41
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  • Designing CMOS Circuits for Switch-Level Testability

    Publication Year: 1987, Page(s):42 - 49
    Cited by:  Papers (64)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6359 KB)

    Conventional testing techniques often fail to be effective for CMOS combinational circuits, since most of their switch-level faults cannot be detected by stuck-at-fault testing. The alternative is to design for testability. The design techniques presented here for fully testable CMOS combinational circuits use a three-pattern test scheme to detect both stuck-open and stuck-on switch-level faults. ... View full abstract»

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  • TTTC 10th Anniversary

    Publication Year: 1987, Page(s):50 - 54
    Cited by:  Papers (1)
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  • Test Technology TC Membership [advertisement]

    Publication Year: 1987, Page(s): 54
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  • D&T Calendar

    Publication Year: 1987, Page(s): 55
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  • D&T Scene

    Publication Year: 1987, Page(s):56 - 59
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  • Industry Briefs

    Publication Year: 1987, Page(s):58 - 59
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  • D&T Standards

    Publication Year: 1987, Page(s): 60
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  • D&T Conferences

    Publication Year: 1987, Page(s):61 - 62
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  • Call for Papers

    Publication Year: 1987, Page(s): 63
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  • New Products Design

    Publication Year: 1987, Page(s):64 - 67
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  • New Products Test

    Publication Year: 1987, Page(s):68 - 70
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  • The Computer Society

    Publication Year: 1987, Page(s): 71
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  • Advertiser/Product Index

    Publication Year: 1987, Page(s): 72
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  • There's More to Board Test Than Just Testing Boards [advertisement]

    Publication Year: 1987, Page(s):72a - 72b
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  • There's More to Board Test Than Just Testing Boards [advertisement]

    Publication Year: 1987, Page(s): 72c
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty