IEEE Design & Test of Computers

Issue 2 • April 1987

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  • IEEE Design & Test of Computers

    Publication Year: 1987, Page(s): c1
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  • The Computer Society of the IEEE

    Publication Year: 1987, Page(s): c2
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  • Editorial Board

    Publication Year: 1987, Page(s): 1
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  • Editorial Board

    Publication Year: 1987, Page(s): 2
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  • D&T Letters

    Publication Year: 1987, Page(s): 3
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  • Test Technology: Testing's Impact on Design And Manufacturing

    Publication Year: 1987, Page(s):4 - 5
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  • Expert System Offers Artificially Intelligent Guidance to Built-In Self-Testing of CMOS Stuck-Open Faults in Hardware Accelerators Built with Systolic Arrays Produced by Silicon Compilers via Simulated Annealing

    Publication Year: 1987, Page(s):6 - 7
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  • D&T Scene

    Publication Year: 1987, Page(s):8 - 9
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  • D&T Standards

    Publication Year: 1987, Page(s):10 - 11
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  • Testing Mixed-Signal Devices

    Publication Year: 1987, Page(s):12 - 20
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7244 KB)

    Testing ISDN devices, which mix analog voice information and digital data, puts special demands on the test system. The ISDN has multiple interfaces with devices that perform a variety of functions. What was usually performed by many individual ICs is now performed by a single ISDN device. Particularly challenging are network interface and device feature tests because the test system must generate... View full abstract»

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  • The Seventeenth International Symposium on Fault-Tolerant Computing

    Publication Year: 1987, Page(s): 21
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  • Timing Accuracy in Modern ATE

    Publication Year: 1987, Page(s):22 - 30
    Cited by:  Papers (5)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6753 KB)

    LSI test systems built in the 1970s had compact, 60-pin test heads that presented devices under test with open wires leading to lumped-capacitive loads. Today's VLSI testers have 256-pin test heads with transmission lines leading from the DUTs to driver-comparator circuits that are as far away as 50 cm. Even though these automatic testers are adjusted to subnanosecond accuracy, reflections within ... View full abstract»

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  • 3 Million Hours, 18 Years And over a Billion Research Dollars Later, ITC'87

    Publication Year: 1987, Page(s): 31
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  • Transition Fault Simulation

    Publication Year: 1987, Page(s):32 - 38
    Cited by:  Papers (247)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6280 KB)

    Delay fault testing is becoming more important as VLSI chips become more complex. Components that are fragments of functions, such as those in gate-array designs, need a general model of a delay fault and a feasible method of generating test patterns and simulating the fault. The authors present such a model, called a transition fault, which when used with parallel-pattern, single-fault propagatio... View full abstract»

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  • Aliasing Errors in Signature in Analysis Registers

    Publication Year: 1987, Page(s):39 - 45
    Cited by:  Papers (60)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5299 KB)

    The authors discuss aliasing errors in signature analysis registers for self-testing networks and review analytical results. The results show that when p, the probability that an error will occur at a network output, is close to 1/2, there is a bound of the aliasing error. The analysis uses a graph to represent the probability of transition, the Markov process, and z-transforms to analyze the beha... View full abstract»

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  • The Effects of Modeling on Simulator Performance

    Publication Year: 1987, Page(s):46 - 54
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6911 KB)

    Gate-level simulators are usually thought of in terms of their benefits to logic designers, while behavioral simulators are considered to be the province of system architects. However, the behavioral modeling capabilities of a multilevel gate/behavioral simulator significantly enhanced the performance and accuracy of what are essentially gate-level simulations. The Behave simulator is a multilevel... View full abstract»

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  • New Products Design

    Publication Year: 1987, Page(s):55 - 56
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  • You May Already Be a Winner [advertisement]

    Publication Year: 1987, Page(s): 56
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  • New Products Test

    Publication Year: 1987, Page(s):57 - 59
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  • Industry Briefs

    Publication Year: 1987, Page(s): 60
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  • D&T Conferences

    Publication Year: 1987, Page(s):61 - 63
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  • Erratum

    Publication Year: 1987, Page(s): 62
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  • Advertiser/Product Index

    Publication Year: 1987, Page(s): 64
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  • IEEE Design & Test of Computers

    Publication Year: 1987, Page(s):64a - 64b
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  • D&T Calendar

    Publication Year: 1987, Page(s): 64c
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty