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IEEE Design & Test of Computers

Issue 5 • Oct. 1986

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  • IEEE Design & Test of Computers

    Publication Year: 1986, Page(s): c1
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  • IEEE Computer Society

    Publication Year: 1986, Page(s): c2
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  • Editorial Board

    Publication Year: 1986, Page(s): 1
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  • Choose LASAR Logic Simulation And Win the Board Game

    Publication Year: 1986, Page(s):2 - 3
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  • Editor Board

    Publication Year: 1986, Page(s): 4
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  • D&T Scene

    Publication Year: 1986, Page(s): 5
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  • D&T Roundtable

    Publication Year: 1986, Page(s):6 - 71
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  • Piercing the Testability Barriers

    Publication Year: 1986, Page(s):7 - 8
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  • D&T Calendar

    Publication Year: 1986, Page(s):8 - 71
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  • Program Highlights

    Publication Year: 1986, Page(s): 9
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  • Uncompromised VLSI Testing the Megaone And Only [advertisement]

    Publication Year: 1986, Page(s): 10
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  • Testability: Barriers to Acceptance

    Publication Year: 1986, Page(s):11 - 15
    Cited by:  Papers (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4973 KB)

    Design for testability sounds wonderful in theory, but if it is not used, or worse used to disadvantage, what good is it? With today's escalating technology and management's fear of commitment to a costly testing program, DFT practices are suffering. the author discusses the prominent barriers to accepting design for test: the impact of more advanced technology, the misunderstood role of testing, ... View full abstract»

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  • From Micro to Mainframe, Casio's Got the Hardware for your Software [advertisement]

    Publication Year: 1986, Page(s): 16
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  • Detecting FET Stuck-Open Faults in CMOS Latches And Flip-Flops

    Publication Year: 1986, Page(s):17 - 26
    Cited by:  Papers (42)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4361 KB)

    The authors present evidence that conventional tests cannot detect FET stuck-open faults in several CMOS latches and flip-flops. Examples are given to show that stuck-open faults can change static latches and flip-flops into dynamic devices¿a danger to circuits whose operation requires static memory, since undetected FET stuck-open faults can cause malfunctions. Designs are given for several memo... View full abstract»

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  • Built-in Self Testing of Embedded Memories

    Publication Year: 1986, Page(s):27 - 37
    Cited by:  Papers (58)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4972 KB)

    The authors present a built-in self-test (BIST) method for testing embedded memories. Two algorithms are proposed for self-testing of embedded bedded RAMs, both of which can detect a large variety of stuck-at and non-stuck-at faults. The hardware implementation of the methods requires a hardware test-pattern generator, which produces address, data, and read/write inputs. The output responses of th... View full abstract»

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  • Now, Your Computer And Communications Network Analysis Simplified [advertisement]

    Publication Year: 1986, Page(s): 38
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  • Software Quality Assurance And CAD User Interfaces

    Publication Year: 1986, Page(s):39 - 48
    Cited by:  Papers (4)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2688 KB)

    The author gives an overview of software quality assurance and its relation to user interfaces for CAD systems. some of the basic concepts as well as the theoretical background and state of the art of software quality assurance are presented. A pragmatic approach to quality assurance of the software for CAD systems is presented by showing its application to a VLSI layout editor. The emphasis is on... View full abstract»

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  • Gould [advertisement]

    Publication Year: 1986, Page(s): 48
    Cited by:  Papers (1)
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  • Computer-Aided-Design Research at the Ge Microelectronics Center

    Publication Year: 1986, Page(s):49 - 56
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3337 KB)

    In late 1980, the GE Microelectronics Center (MEC) was established to develop a proprietary gate array program for infusing JC technology into GE products. One team developed a CAD system helping engineers through the complete design cycle from circuit description capture and simulation to layout, post-layout simulation, processing, and test. Another team developed a gate array CMOS process at the... View full abstract»

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  • New Products Design

    Publication Year: 1986, Page(s):57 - 58
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  • New Products Test

    Publication Year: 1986, Page(s): 59
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  • D&T Conferences

    Publication Year: 1986, Page(s):60 - 63
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  • Design Automation Technical Committee Newsletter

    Publication Year: 1986, Page(s):68 - 69
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  • Book Reviews

    Publication Year: 1986, Page(s): 70
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  • Tutorial - Integrated Services Digital Networks (ISDN) [advertisement]

    Publication Year: 1986, Page(s): 70
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty