IEEE Design & Test of Computers

Issue 4 • Aug. 1986

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  • IEEE Design & Test of Computers

    Publication Year: 1986, Page(s): c1
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  • Test Your Limits [advertisement]

    Publication Year: 1986, Page(s):c2 - 1
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  • The speed of a device tester the power of a board tester [advertisement]

    Publication Year: 1986, Page(s):2 - 3
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  • IEEE Computer Society

    Publication Year: 1986
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  • Editorial Board

    Publication Year: 1986, Page(s): 5
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  • From the Editor-in-Chief

    Publication Year: 1986, Page(s): 6
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  • Finally, a Logic Simulator That Keeps up with the Times [advertisement]

    Publication Year: 1986, Page(s): 7
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  • Dedicated to Change [advertisement]

    Publication Year: 1986, Page(s): 8
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  • Test Technology Newsletter

    Publication Year: 1986, Page(s): 9
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  • D&T Scene

    Publication Year: 1986, Page(s):10 - 11
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  • Erratum

    Publication Year: 1986, Page(s): 11
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  • About the cover …

    Publication Year: 1986, Page(s): 11
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  • Who Do You Suppose Offers the Most Cost-Effective Solution to All Your I.C. Component Testing Needs? [advertisement]

    Publication Year: 1986, Page(s): 12
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  • The Future of Test

    Publication Year: 1986, Page(s):13 - 14
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  • First Call for Participation

    Publication Year: 1986, Page(s): 14
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  • A New Parallel Test Approach for Large Memories

    Publication Year: 1986, Page(s):15 - 22
    Cited by:  Papers (24)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2813 KB)

    Memory test times-and thus test costs-are increasing rapidly as the size of the memories grows each year. Testability techniques therefore must be developed to reduce the test time without compromising the test quality. This article presents an approach that meets this goal using parallel signature analyzers (PSAs). PSAs can access more data cells in parallel than I/O pins can, and the approach's ... View full abstract»

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  • Integrating an Electron-Beam System into VLSI Fault Diagnosis

    Publication Year: 1986, Page(s):23 - 29
    Cited by:  Papers (26)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6130 KB)

    Using design data, the system can prepare a logic-state map for the device under test. The map draws top-layer connections in different colors according to their expected logic states so the map may be compared to the DUT image observed by the electron-beam tester. The system has successfully tested a 75K-transistor VLSI device. View full abstract»

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  • The State of the Art of Integrated Testing [advertisement]

    Publication Year: 1986, Page(s):30 - 31
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  • How to Make a Million Dollars Overnight [advertisement]

    Publication Year: 1986, Page(s): 32
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  • International Test Conference 1986

    Publication Year: 1986, Page(s):itc1 - itc4
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  • Call for Papers ITC '87 Integration of Test with Design And Manufacturing

    Publication Year: 1986, Page(s):itc5 - itc7
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  • Test Week Tutorials

    Publication Year: 1986, Page(s):itc8 - itc11
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (676 KB)

    Summary form only given. Strong light-matter coupling has been recently successfully explored in the GHz and THz [1] range with on-chip platforms. New and intriguing quantum optical phenomena have been predicted in the ultrastrong coupling regime [2], when the coupling strength Ω becomes comparable to the unperturbed frequency of the system ω. We recently proposed a new experimental ... View full abstract»

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  • 1986 Program Overview

    Publication Year: 1986, Page(s):itc12 - itc13
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  • International Test Conference

    Publication Year: 1986, Page(s):itc14 - itc32
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  • Achieving Accurate Timing Measurements on TTL/CMOS Devices

    Publication Year: 1986, Page(s):33 - 42
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3445 KB)

    Production TTL and CMOS timing measurements obtained between different test systems and between test systems and the bench setup often do not correlate or do not appear to be accurate even though the automatic test equipment system has subnanosecond accuracy. Errors of as much as 2 ns can occur with small-, medium-, and large-scale integration and with gate arrays using the new TTL and CMOS techno... View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty