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Design & Test of Computers, IEEE

Issue 4 • Date Aug. 1985

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Displaying Results 1 - 25 of 37
  • IEEE Design & Test of Computers

    Page(s): c1
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  • The Competition Gave Up [advertisement]

    Page(s): c2
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  • Our Logic Simulator Will Help You Make It through the next Revolution

    Page(s): 1
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  • Choose LASAR Logic Simulation And Win the Board Game

    Page(s): 2 - 3
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  • IEEE Computer Society

    Page(s): 4
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  • Editorial Board

    Page(s): 5
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  • Letters to the Editor

    Page(s): 6 - 8
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  • ZZZip through VLSI Design with VERILOG

    Page(s): 9
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  • Artificial Intelligence: Humanizing a "Dumb" Program

    Page(s): 10
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  • Designing VISI Tests Is a Waste of Time [advertisement]

    Page(s): 11
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  • D&T Scene

    Page(s): 12 - 19
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  • Correction

    Page(s): 19
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  • Moving?

    Page(s): 19
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  • IEEE Computer Society Membership Application

    Page(s): 20
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  • Artificial Intelligence Techniques in Design And Test

    Page(s): 21
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  • A Rule-Based System for Optimizing Combinational Logic

    Page(s): 22 - 32
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    SOCRATES is a rule-based expert system that optimizes combinational logic for a specific target technology. The system performs substitutions of equivalent gate configurations, thereby reducing the overall area of the implementation and improving the speed of the design. A control mechanism uses various backup strategies to choose the rules applied to the circuit. Users can easily extend the library of transformation rules through a rule generation module that automatically encodes rules and inserts them into the knowledge base. Timing constraints placed on the circuit can be modified to allow the designer to explore a large design space in a matter of minutes. Implementations generated by the system are comparable in area and speed to circuits designed by experts. View full abstract»

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  • 1984 IEEE Workshop on Languages for Automation November 1-3, 1984

    Page(s): 32
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  • The VLSI Design Automation Assistant: From Algorithms to Silicon

    Page(s): 33 - 43
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (11718 KB)  

    Our ability to fabricate complex VLSI chips is outrunning our ability to design them. To reduce the design time for complex chips we are creating an expert design assistant¿programs that automate as many of the design tasks as possible while allowing the human designer to control the synthesis process. A series of programs translates an algorithm into a chip layout. Some programs are expert systems while others use traditional algorithms. Our early results lead us to believe that a knowledge-based expert system is an appropriate tool for bridging the gap between logical and physical design. View full abstract»

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  • IEEE Design & Test of Computers

    Page(s): 43
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  • Knowledge-Based Code Selection Methods in Retargetable Microcode Synthesis

    Page(s): 44 - 55
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    We have presented a method for machine-independent synthesis of microcode using knowledge-based techniques. A high-level representation of the microprogram is translated into symbolic assertions and then converted by the synthesis system to microcode. Thus, a synthesis system can function as the back end of a microcode compiler. Since the knowledge base is machine-independent and requires only a machine description to generate microcode for that machine, it can also be used as a retargetable microcode compiler. The knowledge base is in procedural form and consists of transformation rules that reflect the effect of MOs on machine states. Many of these rules simply restrict the transformations to acceptable behavior on the part of the synthesis system. Others help to reduce the search by providing knowledge about desirable behavior in the form of heuristics, or help the synthesis system reason about different possible derivations for the same specification. View full abstract»

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  • A Knowledge-Based System for Designing Testable VLSI Chips

    Page(s): 56 - 68
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    The complexity of VLSI circuits has increased the need for design for testability (DFT). Numerous techniques for designing more easily tested circuits have evolved over the years, with particular emphasis on built-in testing approaches. What has not evolved is a design methodology for evaluating and making choices among the numerous existing approaches. This article describes efforts to build a knowledge-based expert system for designing testable VLSI chips. A framework for a methodology incorporating structural, behavioral, qualitative, and quantitative aspects of known DFT techniques is introduced. This methodology provides a designer with a systematic DFT synthesis approach. The process of partitioning a design into subcircuits for individual processing is described and a new concept¿I-path¿is used to transfer data from one place in the circult to another. Rules for applying testable design methodologies to circuit partitions and for evaluating the various solutions obtained are also presented. Finally, a case study using a prototype system is described. View full abstract»

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  • Selected Reprints on Logic Design for Testability 1984 [advertisement]

    Page(s): 68
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  • MIND: An inside Look at an Expert System for Electronic Diagnosis

    Page(s): 69 - 77
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    Because of its intended purpose, it is very complicated to diagnose faults in VLSI test system hardware. When this problem is considered in the hardware design phase, it is apparent that VLSI test systems need to have built-in self-test features. For a self-test to be of any value, the circuit check program should minimize the hardware involved in each test. MIND is an expert system for VLSI test system diagnosis that integrates the principles of their hierarchical design and experts' heuristics to achieve a practical approach to reducing test system downtime. View full abstract»

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  • Proceedings 1984 ACM IEEE Design Automation Conference [advertisement]

    Page(s): 77
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  • Natural-Language Interface for CAD: A First Step

    Page(s): 78 - 86
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (6817 KB)  

    Though the ubiquity of CAD tools in state-of-the-art VLSI design has forced the issue of user interfaces for CAD to prominence, one type of user interface that has not been investigated hitherto is the naturallanquage interface. The CAD domain is substantially more complex than the domains for which previous natural-language interfaces have been built. This implies that a natural-language interface for CAD cannot be based on previous approaches to language understanding; a new approach is required. Our approach emphasizes flexibility, parallelism, and redundancy, and is embodied in an interface called Cleopatra. Ultimately, Cleopatra will be an interface for an ¿integrated design environment.¿ As a first step towards that goal, but also as a useful tool in its own right, Cleopatra currently deals with circuit-simulation post-processing. View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty