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IEEE Design & Test of Computers

Issue 3 • Date June 1985

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Displaying Results 1 - 25 of 38
  • IEEE Design & Test of Computers

    Publication Year: 1985, Page(s): c1
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  • MCNC Releases the VIVID System [advertisement]

    Publication Year: 1985, Page(s): c2
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  • Our Logic Simulator Will Help You Make It through the next Revolution

    Publication Year: 1985, Page(s): 1
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  • Is LASAR Logic Simulation Best? Take This Test [advertisment]

    Publication Year: 1985, Page(s):2 - 3
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  • IEEE Computer Society

    Publication Year: 1985, Page(s): 4
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  • Editorial Board

    Publication Year: 1985, Page(s): 5
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  • [Advertisement]

    Publication Year: 1985, Page(s): 6
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  • 100% VLSI Fault Grading Is No Longer an Imaginary Goal. It's a Reality

    Publication Year: 1985, Page(s): 7
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  • From the Editor-in-Chief

    Publication Year: 1985, Page(s):8 - 9
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  • D&T Scene

    Publication Year: 1985, Page(s):10 - 15
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  • Structure Level Tools [advertisement]

    Publication Year: 1985, Page(s): 16
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  • Design Automation for the Right Side of the Brain [advertisement]

    Publication Year: 1985, Page(s): 17
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  • The Economics of Test

    Publication Year: 1985, Page(s):18 - 19
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  • Low-Cost Testers: Are They Really Low Cost?

    Publication Year: 1985, Page(s):20 - 28
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9382 KB)

    Initial ATE capital investments can affect overall test manufacturing costs as shown in this analysis, which compares a $5000 semiconductor tester with a $900,000 system (purchase price). The application is wafer testing of logic die, and the product has a five-year lifetime. Variables affecting cost include tester throughput, wafer test escape rate, and test system capital cost. Factors considere... View full abstract»

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  • A Basis for Setting Burn-in Yield Criteria

    Publication Year: 1985, Page(s):29 - 34
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (6033 KB)

    This simple, useful, and practical approach to assess the cost benefits from using burned-in plastic ICs assumes a simple approximation for early life failure during burn-in and predicts the failure rate of the residual parts on the basis of yield percentage. Because product applications, end-user environment, and device quality vary, the simplicity of this method is obtained at the cost of some r... View full abstract»

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  • Proceedings 1984 ACM IEEE Design Automation Conference [advertisement]

    Publication Year: 1985, Page(s): 34
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  • A Fault-Driven, Comprehensive Redundancy Algorithm

    Publication Year: 1985, Page(s):35 - 44
    Cited by:  Papers (78)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9207 KB)

    This article describes a fault-driven algorithm that generates all possible repair solutions for a given bit failure pattern in a redundant RAM. Benefits of this approach include the ability to select repair solutions based on userdefined preferences (for example, fewest total elements invoked or fewest rows invoked). Perhaps the greatest advantage of this algorithm is its ability to generate solu... View full abstract»

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  • IEEE Design & Test of Computers

    Publication Year: 1985, Page(s): 44
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  • Exploratory Data Analysis for Semiconductor Manufacturing

    Publication Year: 1985, Page(s):45 - 55
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (10242 KB)

    This article introduces a few modern statistical techniques that are especially well suited to analysis of data obtained from semiconductor testing. Test data is particularly likely to be distributed in non-Gaussian fashion, thus data summaries and displays based on sample means and standard deviations are likely to be misleading. Engineers¿test engineers in particular¿should become familiar wit... View full abstract»

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  • 1984 IEEE Workshop on Languages for Automation November 1-3,1984

    Publication Year: 1985, Page(s): 55
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  • Codec Testing Using Synchronized Analog And Digital Signals

    Publication Year: 1985, Page(s):56 - 63
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7821 KB)

    Five methods for verifying coder/decoder operation in telecommunications PC boards provide the engineer optimal fault coverage with minimal test time. All methods support a dual-purpose testing strategy: (1) to conduct an in-circuit board test to detect assembly errors before a functional test and (2) to conduct a functional test in which stress is applied to detect marginal performance. All metho... View full abstract»

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  • Goalie: A Space Efficient System for VLSI Artwork Analysis

    Publication Year: 1985, Page(s):64 - 72
    Cited by:  Papers (25)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (10202 KB)

    Advances in VLSI have resulted in more and more complex circuitry, fueling the need for programs that analyze IC mask artwork. This article describes Goalie, an artwork analysis system, by explaining the algorithms used to support circuit extraction, Boolean geometric operations, connectivity analysis, capacitance measurement and design checking. Tests on several systems have shown that Goalie run... View full abstract»

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  • D&T Interview

    Publication Year: 1985, Page(s):73 - 80
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  • D&T Conferences

    Publication Year: 1985, Page(s):81 - 86
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  • 1984 Academic Forum for Test Technology October 19, 1984

    Publication Year: 1985, Page(s): 86
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty