IEEE Design & Test of Computers

Issue 2 • April 1985

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  • IEEE Design & Test of Computers

    Publication Year: 1985, Page(s): c1
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  • The Challenge: To Create Multilevel Behavioral Simulation. The Answer: HELIX [advertisement]

    Publication Year: 1985, Page(s): c2
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  • 1984: Mentor Graphics Leads World CAE Sales

    Publication Year: 1985, Page(s): 1
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  • Is LASAR Logic Simulation Best? Take This Test [advertisment]

    Publication Year: 1985, Page(s):2 - 3
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  • IEEE Computer Society

    Publication Year: 1985, Page(s): 4
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  • Editorial Board

    Publication Year: 1985, Page(s): 5
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  • Expert for PCB Design [advertisement]

    Publication Year: 1985, Page(s):6 - 7
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  • D&T Guest Editorial

    Publication Year: 1985, Page(s):8 - 10
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  • D&T Scene

    Publication Year: 1985, Page(s):10 - 16
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  • Proceedings: 1983 International Test Conference, October 1983 [advertisement]

    Publication Year: 1985, Page(s): 15
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  • Moving?

    Publication Year: 1985, Page(s): 16
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  • Built-In Self-Test: Pass or Fail?

    Publication Year: 1985, Page(s):17 - 19
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  • The Challenge of the next Generation... [advertisement]

    Publication Year: 1985, Page(s): 20
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  • Built-In Self-Test Techniques

    Publication Year: 1985, Page(s):21 - 28
    Cited by:  Papers (220)  |  Patents (20)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (7505 KB)

    A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the p... View full abstract»

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  • Built-In Self-Test Structures

    Publication Year: 1985, Page(s):29 - 36
    Cited by:  Papers (58)  |  Patents (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8717 KB)

    A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the p... View full abstract»

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  • Back Issues

    Publication Year: 1985, Page(s): 36
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  • Implementing a Built-In Self-Test PLA Design

    Publication Year: 1985, Page(s):37 - 48
    Cited by:  Papers (62)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (14785 KB)

    An NMOS implementation of a new built-in self-test PLA design is presented. The layouts for its additional test circuitry result in appoximately 15-percent overhead for most large PlAS, a significantly better overhead than that of any existing scheme. Both the input test patterns and the output responses, which are compressed intoastring of parity bits, are independent of the functions that the PL... View full abstract»

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  • Advance Registration

    Publication Year: 1985, Page(s): 49
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  • Self-Tested Data Flow Logic: A New Approach

    Publication Year: 1985, Page(s):50 - 58
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (9561 KB)

    The article describes a new approach to the self-testing and testability analysis of the types of logic structure encountered in the data flow paths of computers. The main purpose of the new methodology is to avoid the costs associated with manual or automatic test pattern generation. Instead of relying upon an automated process of scanning through a gatelevel description of the logic, this is an ... View full abstract»

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  • Proceedings: 1984 International Conference on Computer Design, October 1984 [advertisement]

    Publication Year: 1985, Page(s): 58
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  • Test Length in a Self-Testing Environment

    Publication Year: 1985, Page(s):59 - 63
    Cited by:  Papers (56)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5950 KB)

    Two ideas are Coupled to help determine the Pseudorandom test length in a self-testing environment. The first is that yield, defect level after test, and test coverage are related. Tbe second is that Fault Coverage as ta function of the number of pseudorandom test patterns can be approximated on semilogarithmic paper an exponential curve, with statistical confidence intervals. Merging these two co... View full abstract»

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  • IEEE Design&Test of Computers

    Publication Year: 1985, Page(s): 63
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  • Built-In Self-Test Trends in Motorola Microprocessors

    Publication Year: 1985, Page(s):64 - 71
    Cited by:  Papers (38)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (5903 KB)

    The first built-in self-test feature in a Motorola sidered a "wart" until a RAM test application recast it as a "feature." Though the BIST approach-an idea conceived as a way to reduce production costs for the MC6805 family-did not meet its major design objective, the experience provided impetus for the development of BIST techniques for the MC6804P2, which met most of the objectives intended for ... View full abstract»

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  • [Advertisement]

    Publication Year: 1985, Page(s): 72
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  • 100% VLSI Fault Grading Is No Longer an Imaginary Goal. It's a Reality

    Publication Year: 1985, Page(s): 73
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty