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Design & Test of Computers, IEEE

Issue 1 • Date Feb. 1985

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Displaying Results 1 - 25 of 35
  • IEEE Design & Test of Computers

    Page(s): c1
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  • The Challenge: To Create Multilevel Behavioral Simulation. The Answer: HELIX [advertisement]

    Page(s): c2
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  • How to Make a PC Board Fly [advertisement]

    Page(s): 1
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  • Is LASAR Logic Simulation Best? Take This Test [advertisment]

    Page(s): 2 - 3
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  • IEEE Computer Society

    Page(s): 4
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  • Editorial Board

    Page(s): 5
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  • [Advertisement]

    Page(s): 6
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  • 100% VLSI Fault Grading Is No Longer an Imaginary Goal. It's a Reality

    Page(s): 7
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  • D&T Scene

    Page(s): 8 - 12
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  • Proceedings: 1983 International Test Conference, October 1983 [advertisement]

    Page(s): 11
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  • Proceedings: 1984 International Conference on Computer Design, October 1984 [advertisement]

    Page(s): 12
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  • 1985 IEEE Microprocessor Forum

    Page(s): 13
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  • Expert for PCB Design [advertisement]

    Page(s): 14 - 15
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  • Design Automation

    Page(s): 16 - 17
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  • Shortcut to Success [advertisement]

    Page(s): 18
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  • The Magic VLSI Layout System

    Page(s): 19 - 30
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    Magic is a new IC layout system that includes several facilities traditionally contained in separate batch-processing programs. Magic incorporates expertise about design rules, connectivity, and routing directly into the layout editor and uses this information to provide several unusual features. They include a continuous design-rule checker that operates in background and maintains an up-to-date picture of violations; a hierarchical circuit extractor that only re-extracts portions of the circuit that have changed; an operation called plowing that permits interactive stretching and compaction; and a suite of routing tools that can work under and around existing connections in the channels. A design style called logs and a data structure called corner stitching are used to achieve an efficient implementation of the system. View full abstract»

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  • Hierarchical Layout Verification

    Page(s): 31 - 37
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    This article presents a hierarchical cell structure that has been Used successfully to improve the performance of Intel's connectivity verifier and design rule checker. A unique algorithm for performing design rule checks efficiently in a hierarchical environment is discussed in detail. To undersize and oversize in a hierarchical environment without disrupting the cell structure, the definition of sizing must be changed so that geometries inside a cell and touching the cell boundaries do not pull away and geometries outside the cell do not extend inside. There are also a few Pathologies¿caused mostly by looking at only a small portion of the layout, outside of the context where it is used. Nevertheless, careful use of hierarchical design can deliver order-of-magnitude improvements in layout checking runtime. View full abstract»

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  • Statistical Fault Analysis

    Page(s): 38 - 44
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (5958 KB)  

    Statistical Fault Analysis, or Stafan, is proposed as an alternative to fault simulation of digital circuits. This method defines Controllabilities and observabilities of circuit nodes as probabilities estimated from signal statistics of fault-free simulation. Special Procedures deal with these quantities at fanout and feedback nodes. The computed probabilities are used to derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors. Among Stafan's advantages, fault coverage and the undetected fault data obtained for actual circuits are shown to agree within five percent of fault simulator results, yet CPU time and memory demands fall far short of those required in fault simulation. The Computational complexity added to a fault-free simulator by Stafan grows only linearly with the number of circuit nodes. View full abstract»

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  • The Redesign System: A Knowledge-Based Approach to VLSI CAD

    Page(s): 45 - 54
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    Artificial intelligence techniques offer one possible avenue toward new CAD tools to handle the complexities of VLSI. Redesign is a Prototype knowledge-based system that uses Al techniques to interactively aid in the functional redesign of digital circuits. Given a desired change in the function of a circuit, Redesign combines rule-based knowledge of design tactics with its ability to analyse signal propagation through circuits, in order to help the user focus on an appropriate portion of the circuit to redesign, suggest local redesign alternatives, and determine side effects of possible redesigns. Using lessons learned from work on Redesign, we are working on systems to aid in designing and debugging VLSI. View full abstract»

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  • Toward a Standard Hardware Description Language

    Page(s): 55 - 62
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    A hardware description language should be simple, expressive, orthogonal, easy to read, and extendable. It should have associated efficient, user-friendly tools that produce good results, and it should have functional, structural and layout semantics. Zeus satisfies most of these requirements and therefore its features should be included in any HDL proposed as a standard. Zeus and its recent developments¿its close integration with Modula-2 and its implementation in the context of a metaprogramming environment¿are presented here. Two example circuits, a comparator circuit and a music generation circuit, illustrate some essential features of Zeus. A number of CAD tools that will use Zeus are under development, and Zeus has been benchmarked with over 40 design examples. View full abstract»

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  • EDIF: A Mechanism for the Exchange of Design Information

    Page(s): 63 - 69
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    The need for a standard format for the interchange of electronic design information has become critical. Past efforts to standardize have failed or have only partially succeeded for a variety of reasons. The proponents of four such efforts formed a committee in late 1983 to cull the best from their previous work and propose a unified format as a standard. The Electronic Design Interchange Format, EDIF, initially targets information exchange between designer and foundry. Macro cells, net lists, schematics, layout information, and stimulus/response information can be expressed in EDIF version 1.0. As the original committee continues its development activity, several subcommittees of experts address behavioral description, testing, technology, procedural layout, and printed circuit boards. View full abstract»

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  • Computer-Aided Design Databases

    Page(s): 70 - 74
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  • Proceedings: 1984 International Test Conference, October 1984 [advertisement]

    Page(s): 73
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  • D&T Conferences

    Page(s): 75 - 79
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  • D&T Standards

    Page(s): 80 - 81
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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief
Krishnendu Chakrabarty