IEEE Computer Architecture Letters

Issue 2 • Feb. 2006

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Displaying Results 1 - 7 of 7
  • Papers 
  • Exploiting Narrow Values for Soft Error Tolerance

    Publication Year: 2006, Page(s): 12
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (417 KB) | HTML iconHTML

    Soft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. In this paper we propose simple mechanisms that effectively reduce the vulnerability to soft errors In a processor. Our designs are generally motivated by the fact that many of... View full abstract»

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  • A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator

    Publication Year: 2006, Page(s): 13
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (203 KB) | HTML iconHTML

    Modern programming languages often include complex mechanisms for dynamic memory allocation and garbage collection. These features drive the need for more efficient implementation of memory management functions, both in terms of memory usage and execution performance. In this paper, we introduce a software and hardware co-design to improve the speed of the software allocator used in free-BSD syste... View full abstract»

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  • An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation

    Publication Year: 2006, Page(s): 14
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (92 KB) | HTML iconHTML

    Multiple core designs have become commonplace in the processor market, and are hence a major focus in modern computer architecture research. Thus, for both product development and research, multiple core processor simulation environments are necessary. A well-known positive feedback property of computer design is that we use today's computers to design tomorrow's. Thus, with the emergence of chip ... View full abstract»

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  • Disintermediated Active Communication

    Publication Year: 2006, Page(s): 15
    Cited by:  Papers (2)  |  Patents (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (224 KB) | HTML iconHTML

    Disintermediated active communication (DAC) is a new paradigm of communication in which a sending thread actively engages a receiving thread when sending it a message via shared memory. DAC is different than existing approaches that use passive communication through shared-memory - based on intermittently checking for messages - or that use preemptive communication but must rely on intermediaries ... View full abstract»

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  • User-Driven Frequency Scaling

    Publication Year: 2006, Page(s): 16
    Cited by:  Papers (14)  |  Patents (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (315 KB) | HTML iconHTML

    We propose and evaluate user-driven frequency scaling (UDFS) for improved power management on processors that support dynamic voltage and frequency scaling (DVFS), e.g, those used in current laptop and desktop computers. UDFS dynamically adapts CPU frequency to the individual user and the workload through a simple user feedback mechanism, unlike currently-used DVFS methods which rely only on CPU u... View full abstract»

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  • Subtleties of transactional memory atomicity semantics

    Publication Year: 2006
    Cited by:  Papers (27)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (99 KB) | HTML iconHTML

    Transactional memory has great potential for simplifying multithreaded programming by allowing programmers to specify regions of the program that must appear to execute atomically. Transactional memory implementations then optimistically execute these transactions concurrently to obtain high performance. This work shows that the same atomic guarantees that give transactions their power also have u... View full abstract»

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  • A Case for Compressing Traces with BDDs

    Publication Year: 2006, Page(s): 18
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (189 KB) | HTML iconHTML

    Instruction-level traces are widely used for program and hardware analysis. However, program traces for just a few seconds of execution are enormous, up to several terabytes in size, uncompressed. Specialized compression can shrink traces to a few gigabytes, but trace analyzers typically stream the decompressed trace through the analysis engine. Thus, the complexity of analysis depends on the deco... View full abstract»

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Aims & Scope

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. 

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Meet Our Editors

Editor-in-Chief
Daniel J. Sorin
Duke University
Electrical & Computer Engineering
PO Box 90291
Durham, NC 27708
e-mail: sorin@ee.duke.edu