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# IEEE Transactions on Circuits and Systems II: Express Briefs

## Filter Results

Displaying Results 1 - 25 of 28

Publication Year: 2007, Page(s):C1 - C4
| PDF (42 KB)
• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2007, Page(s): C2
| PDF (38 KB)
• ### Editorial: One Year at the Helm

Publication Year: 2007, Page(s):1 - 3
| PDF (226 KB) | HTML
• ### A Low-Power Wideband CMOS LNA for WiMAX

Publication Year: 2007, Page(s):4 - 8
Cited by:  Papers (59)
| | PDF (202 KB) | HTML

In this brief, the design of a low-power inductorless wideband low-noise amplifier (LNA) for worldwide interoperability for microwave access covering the frequency range from 0.1 to 3.8 GHz using 0.13-mum CMOS is described. The core consumes 1.9 mW from a 1.2-V supply. The chip performance achieves S11 below -10 dB across the entire band and a minimum noise figure of 2.55 dB. The simula... View full abstract»

• ### Design of High-Order Phase-Lock Loops

Publication Year: 2007, Page(s):9 - 13
Cited by:  Papers (15)  |  Patents (1)
| | PDF (217 KB) | HTML

The analysis, and design of third-order, (and higher) phase-locked loops (PLL) is difficult. This paper presents a novel approach to overcome these difficulties by allowing high-order loops to be viewed as a natural extension of lower order ones. This is accomplished by adding nested first-order feedback loops around a basic first-order loop filter. Our approach will also be related to the concept... View full abstract»

• ### An Output Buffer for 3.3-V Applications in a 0.13-$muhbox{m}$ 1/2.5-V CMOS Process

Publication Year: 2007, Page(s):14 - 18
Cited by:  Papers (18)
| | PDF (973 KB) | HTML

With a 3.3-V interface, such as PCI-X application, high-voltage overstress on the gate oxide is a serious reliability problem in designing I/O circuits by using only 1/2.5-V low-voltage devices in a 0.13-mum CMOS process. Thus, a new output buffer realized with low-voltage (1- and 2.5-V) devices to drive high-voltage signals for 3.3-V applications is proposed in this paper. The proposed output buf... View full abstract»

• ### Design of a Sample-Rate Converter From CD to DAT Using Fractional Delay Allpass Filter

Publication Year: 2007, Page(s):19 - 23
Cited by:  Papers (8)
| | PDF (394 KB) | HTML

In sampling rate conversion between two different formats, the desired output sample values are the interpolated sample values at noninteger (or, integer) multiples of the original sampling period. In this brief, we present an efficient structure for sampling rate conversion from 44.1-kHz compact disc to 48-kHz digital audio tape formats. For efficient conversion, we propose a new infinite-impulse... View full abstract»

• ### Variable Digital Filter With Least-Square Criterion and Peak Gain Constraints

Publication Year: 2007, Page(s):24 - 28
Cited by:  Papers (17)
| | PDF (534 KB) | HTML

Variable digital filters are useful for various signal processing and communication applications where the frequency characteristics, such as fractional delays and cutoff frequencies, can be varied online. In this brief, we present a formulation that allows the tradeoff between the total squared error and the maximum deviation from the desired response in the passband and stopband. With this formu... View full abstract»

• ### Switched-Capacitor Multiply-By-Two Amplifier Insensitive to Component Mismatches

Publication Year: 2007, Page(s):29 - 33
Cited by:  Papers (6)  |  Patents (3)
| | PDF (227 KB) | HTML

This brief describes a new mismatch-insensitive amplifier with an accurate gain of two and with the parasitic effects compensated. It is based on associating four sets of two capacitors in series during the amplification phase. The amplifier operates within a single clock cycle and uses only one amplifier. A detailed study of the different nonideal effects is presented. Simulated results demonstra... View full abstract»

• ### A Time-Constant Calibrated Phase-Locked Loop With a Fast-Locked Time

Publication Year: 2007, Page(s):34 - 37
Cited by:  Papers (7)
| | PDF (843 KB) | HTML

A time-constant calibrated phase-locked loop with a fast-locked time is presented. A variable capacitance multiplier (VCM) is developed to adjust the equivalent capacitance in the loop filter. And a calibration circuit is used to allow the time constant of the loop filter to track with the reference clock. By using the proposed time-constant calibration circuit and the VCM, the fast acquisition ti... View full abstract»

• ### 1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18-$muhbox{m}$ CMOS Technology

Publication Year: 2007, Page(s):38 - 42
Cited by:  Papers (12)  |  Patents (1)
| | PDF (1605 KB) | HTML

A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated oscillators to align the clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated oscillator reset-phase control scheme causes the starting phase of gated oscillators to alternate repeatedly between 0deg and... View full abstract»

• ### An Affine Projection Adaptive Filtering Algorithm With Selective Regressors

Publication Year: 2007, Page(s):43 - 46
Cited by:  Papers (34)
| | PDF (173 KB) | HTML

We present a novel affine projection algorithm which reduces complexity by selecting a subset of input regressors at every iteration. The optimal selection of input regressors is derived by comparing the cost functions based on the principle of minimum disturbance. The proposed algorithm shows good convergence performance with various experimental results View full abstract»

• ### Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes

Publication Year: 2007, Page(s):47 - 51
Cited by:  Papers (14)  |  Patents (1)
| | PDF (715 KB) | HTML

An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage bulk CMOS process is proposed in this work. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS pr... View full abstract»

• ### Blind Bi-Level Image Restoration With Iterated Quadratic Programming

Publication Year: 2007, Page(s):52 - 56
Cited by:  Papers (21)
| | PDF (664 KB) | HTML

Many camera systems are dedicated to the capture of bi-level objects, including documents, bar codes, handwritten signatures, and vehicle license plates. Degradations in the imaging systems, however, cause blurring to the output images and introduce many more intensity levels. The blurring often arises from the optical aberrations and motions between the object and the camera, and hampers any comp... View full abstract»

• ### Two-Dimensional Antisymmetric Linear Phase Filter Bank Construction Using Symmetric Completion

Publication Year: 2007, Page(s):57 - 60
Cited by:  Papers (4)
| | PDF (111 KB) | HTML

For a given antisymmetric linear phase (LP) filter in two dimensions, an approach that can parameterize the counterpart filter such that they can form a perfect reconstruction filter bank (FB) is proposed. This approach is motivated by a previous work and remedies the incomplete solution there. To illustrate its incompleteness, classification of LP perfect reconstruction FBs is introduced. Possibi... View full abstract»

• ### Analyzing Chaotic Spectra of DC–DC Converters Using the Prony Method

Publication Year: 2007, Page(s):61 - 65
Cited by:  Papers (16)
| | PDF (304 KB) | HTML

When dc-dc converters operate in chaotic modes, they can generate spread spectra, which are useful for reducing the electromagnetic interference (EMI). Conventionally, the Fast Fourier Transform (FFT) is used to analyze the spectra. However, it is not applicable to the inner-harmonics, the nonintegral multiples of the fundamental frequency, which is a prominent feature of chaotic signals. In this ... View full abstract»

• ### Propagation Delay of an RC-Chain With a Ramp Input

Publication Year: 2007, Page(s):66 - 70
Cited by:  Papers (12)
| | PDF (278 KB) | HTML

In this brief, two simple semi-analytical models which allow the estimation of the propagation delay of an RC-chain with a linear input are presented. The closed-form models can be used to evaluate the propagation delay of wires in modern VLSI and ULSI processes. The two approximations, a continuous function and a piecewise function, exhibit a maximum error lower than 15% at the end of the chain. ... View full abstract»

• ### Discrete Lattice Wavelet Transform

Publication Year: 2007, Page(s):71 - 75
Cited by:  Papers (5)
| | PDF (181 KB) | HTML

The discrete wavelet transform (DWT) has gained a wide acceptance in denoising and compression coding of images and signals. In this work we introduce a discrete lattice wavelet transform (DLWT). In the analysis part, the lattice structure contains two parallel transmission channels, which exchange information via two crossed lattice filters. For the synthesis part we show that the similar lattice... View full abstract»

• ### A Constant-$g_{m}$ Constant-Slew-Rate Rail-to-Rail Input Stage With Static Feedback and Dynamic Current Steering for VLSI Cell Libraries

Publication Year: 2007, Page(s):76 - 80
Cited by:  Papers (10)
| | PDF (708 KB) | HTML

A constant-gm input stage featuring both constant small signal and large signal behaviors over the entire input common-mode range is proposed in this brief. A novel static feedback loop is employed to minimize the N and P transconductance mismatch due to process and temperature variations. The output currents of the N and P differential pairs are dynamically steered to keep a constant g... View full abstract»

• ### Nighttime Vehicle Distance Measuring Systems

Publication Year: 2007, Page(s):81 - 85
Cited by:  Papers (13)
| | PDF (302 KB) | HTML

In this brief, a nighttime vehicle distance measuring system using charge-coupled device (CCD) cameras is proposed. The authors use the proportionality of similar triangles to measure the distance between a CCD camera and taillights of a vehicle in front. At night, the taillights form two bright spots in the CCD image, therefore producing two measurable signals. A circuit for counting the number o... View full abstract»

• ### Design of 1-D Stable Variable Fractional Delay IIR Filters

Publication Year: 2007, Page(s):86 - 90
Cited by:  Papers (14)
| | PDF (392 KB) | HTML

In this brief, a two-stage approach for the design of 1-D stable variable fractional delay infinite-impulse response (IIR) digital filters is proposed. In the first stage, a set of fixed delay stable IIR filters are designed by minimizing a quadratic objective function, which is defined by integrating error criterion with IIR filter stability constraint condition. Then, the final design is determi... View full abstract»

• ### 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

Publication Year: 2007, Page(s): 91
| PDF (617 KB)
• ### 2007 International Conference on Multimedia & Expo (ICME)

Publication Year: 2007, Page(s): 92
| PDF (574 KB)
• ### Special issue on systems biology

Publication Year: 2007, Page(s): 93
| PDF (146 KB)
• ### Special issue on multimedia data mining

Publication Year: 2007, Page(s): 94
| PDF (111 KB)

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org