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Circuits and Systems I: Regular Papers, IEEE Transactions on

Issue 1 • Date Jan. 2007

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Displaying Results 1 - 25 of 33
  • Table of contents

    Page(s): C1 - C4
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—I: Regular Papers publication information

    Page(s): C2
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  • Welcome to the Special Section on Smart Sensors!

    Page(s): 1 - 3
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  • A CMOS 3-D Imager Based on Single Photon Avalanche Diode

    Page(s): 4 - 12
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    A 64-pixel linear array aimed at 3-D vision applications is implemented in a high-voltage 0.8 mum CMOS technology. The detection of the incident light signals is performed using photodiodes biased above breakdown voltage so that an extremely high sensitivity can be achieved exploiting the intrinsic multiplication effect of the avalanche phenomenon. Each 38times180-mum2 pixel includes, besides the single photon avalanche diode, a dedicated read-out circuit for the arrival-time estimation of incident light pulses. To increase the distance measurement resolution a multiple pulse measurement is used, extracting the mean value of the light pulse arrival-time directly in each pixel; this innovative approach dramatically reduces the dead-time of the pixel read-out, allowing a high frame rate imaging to be achieved. The sensor array provides a range map from 2 m to 5 m with a precision better than plusmn0.75% without any external averaging operation. Moreover, with the same chip, we have explored for the first time the implementation of an indirect time-of-flight measurement by operating the proposed active pixel in the photon counting mode View full abstract»

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  • Adaptive-Quantization Digital Image Sensor for Low-Power Image Compression

    Page(s): 13 - 25
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    The recent emergence of new applications in the area of wireless video sensor network and ultra-low-power biomedical applications (such as the wireless camera pill) have created new design challenges and frontiers requiring extensive research work. In such applications, it is often required to capture a large amount of data and process them in real time while the hardware is constrained to take very little physical space and to consume very little power. This is only possible using custom single-chip solutions integrating image sensor and hardware-friendly image compression algorithms. This paper proposes an adaptive quantization scheme based on boundary adaptation procedure followed by an online quadrant tree decomposition processing enabling low power and yet robust and compact image compression processor integrated together with a digital CMOS image sensor. The image sensor chip has been implemented using 0.35-mum CMOS technology and operates at 3.3 V. Simulation and experimental results show compression figures corresponding to 0.6-0.8 bit per pixel, while maintaining reasonable peak signal-to-noise ratio levels and very low operating power consumption. In addition, the proposed compression processor is expected to benefit significantly from higher resolution and Megapixels CMOS imaging technology View full abstract»

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  • Focal-Plane Spatially Oversampling CMOS Image Compression Sensor

    Page(s): 26 - 34
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    Image compression algorithms employ computationally expensive spatial convolutional transforms. The CMOS image sensor performs spatially compressing image quantization on the focal plane yielding digital output at a rate proportional to the mere information rate of the video. A bank of column-parallel first-order incremental DeltaSigma-modulated analog-to-digital converters (ADCs) performs column-wise distributed focal-plane oversampling of up to eight adjacent pixels and concurrent weighted average quantization. Number of samples per pixel and switched-capacitor sampling sequence order set the amplitude and sign of the pixel coefficient, respectively. A simple digital delay and adder loop performs spatial accumulation over up to eight adjacent ADC outputs during readout. This amounts to computing a two-dimensional block matrix transform with up to 8times8-pixel programmable kernel in parallel for all columns. Noise shaping reduces power dissipation below that of a conventional digital imager while the need for a peripheral DSP is eliminated. A 128times128 active pixel array integrated with a bank of 128 DeltaSigma-modulated ADCs was fabricated in a 0.35-mum CMOS technology. The 3.1 mm times 1.9-mm prototype captures 8-bit digital video at 30 frames/s and yields 4 GMACS projected computational throughput when scaled to HDTV 1080i resolution in discrete cosine transform (DCT) compression View full abstract»

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  • Bio-Inspired Computer Fovea Model Based on Hexagonal-Type Cellular Neural Network

    Page(s): 35 - 47
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    For decades, numerous scientists have examined the following questions: "How do humans see the world?" and "How do humans experience vision?" To answer these questions, this study proposes a computer fovea model based on hexagonal-type cellular neural network (hCNN). Certain biological mechanisms of a retina can be simulated using an in-state-of-art architecture named CNN. Those biological mechanisms include the behaviors of the photoreceptors, horizontal cells, ganglions, and bipolar cells, and their co-operations in the retina. Through investigating the model and the abilities of the CNN, various properties of the human vision system can be simulated. The human visual system possesses numerous interesting properties, which provide natural methods of enhancing visual information. Various visual information enhancing algorithms can be developed using these properties and the proposed model. The proposed algorithms include color constancy, image sharpness, and some others. This study also discusses how the proposed model works for video enhancement and demonstrates it experimentally View full abstract»

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  • AER EAR: A Matched Silicon Cochlea Pair With Address Event Representation Interface

    Page(s): 48 - 59
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    In this paper, we present an analog integrated circuit containing a matched pair of silicon cochleae and an address event interface. Each section of the cochlea, modeled by a second-order low-pass filter, is followed by a simplified inner hair cell circuit and a spiking neuron circuit. When the neuron spikes, an address event is generated on the asynchronous data bus. We present the results of the chip characterization and the results of an interaural time difference based sound localization experiment using the address event representation (AER) EAR. The chip was fabricated in a 3-metal 2-poly 0.5-mum CMOS process View full abstract»

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  • Analog VLSI Circuit Implementation of an Adaptive Neuromorphic Olfaction Chip

    Page(s): 60 - 73
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    In this paper, we present the analog circuit design and implementation of the components of an adaptive neuromorphic olfaction chip. A chemical sensor array employing carbon black composite sensing materials with integrated signal processing circuitry forms the front end of the chip. The sensor signal processing circuitry includes a dc offset cancellation circuit to ameliorate loss of measurement range associated with chemical sensors. Drawing inspiration from biological olfactory systems, the analog circuits used to process signals from the on-chip odor sensors make use of temporal "spiking" signals to act as carriers of odor information. An on-chip spike time dependent learning circuit is integrated to dynamically adapt weights for odor detection and classification. All the component subsystems implemented on chip have been successfully tested in silicon View full abstract»

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  • A Neuromorphic VLSI Model of Bat Interaural Level Difference Processing for Azimuthal Echolocation

    Page(s): 74 - 88
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    Bats use the unusual sensory modality of echolocation to fly in complete darkness with speed and agility through complex three-dimensional environments. Their small head size and the use of high-frequency sound make interaural level differences (ILDs) their primary cue for azimuthal echolocation. In this paper, we present a neuromorphic VLSI-based system that emulates the ILD processing in the bat brainstem and midbrain. By selecting simple neural units, we propose a circuit model that is mathematically tractable and captures the essential elements of bat ILD computation. The chip includes a three-layer network of spiking neurons with 32 neurons on each layer, and the address-event representation for external interface. Emphasizing the neural spike timing and population behavior, we hope this study will contribute to the bat research community in particular as well as neuroscience in general by providing a real-time, fine-grained, neuromorphic bat echolocation simulator that will be used to address system-level performance of low-level neural algorithms. By developing functional models of the bat echolocation system, we hope to emulate the efficient implementation demonstrated by nature View full abstract»

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  • Integrated Circuit Biosensors Using Living Whole-Cell Bioreporters

    Page(s): 89 - 98
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    A low-power CMOS bioluminescent bioreporter integrated circuit (BBIC) is designed and fabricated for use in electronic/biological chemical sensing. The bioreporters are placed on a CMOS integrated circuit (IC) that detects bioluminescence, performs signal processing and produces a digital output pulse with a frequency that is proportional to the concentration of the target substance. The digital output pulse that contains the sensor information can then be transmitted to a remote location either wirelessly or via a data cable. The basic building blocks of the integrated circuit are the microluminometer and the transmitter. The microluminometer includes an integrated photodetector and a signal processor and is housed in a rugged inexpensive package that can be used in many remote applications in hazardous environmental monitoring. The total power consumption of the entire signal processing circuitry including the photodiodes is 3 mW from a 3.3-V power supply. This is lowered by a factor of 3 when compared to previous versions of the BBIC. In addition, it also integrates all features of detection, processing and data transmission into one small element. The bioreporter typically contains the luxCDABE reporter genes. The close proximity of the bioreporter and the sensing element eliminates the need for complex instrumentation to channel light from the bioreporters to the microluminometer. This paper presents an integrated CMOS microluminometer realized in 0.35-mum CMOS process and optimized for the detection of low-level bioluminescence as part of the BBIC. A flow-through test system was designed to expose the BBIC system composed of the microluminometer and the bioreporter Pseudomonas fluorescens 5RL to salicylate for determination of analytical benchmark data. The results obtained from the experiment are currently being used to study enclosures and micro-environment configurations for field-deployable BBICs for environmental monitoring View full abstract»

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  • Hybrid Integration of an Active Pixel Sensor and Microfluidics for Cytometry on a Chip

    Page(s): 99 - 110
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    Reported are motivations and approaches for the integration of custom sensors with microfluidic devices for cytometry on a chip and related fluid metering applications. To demonstrate, details of a digital 16-element mixed-signal CMOS active pixel optical sensor with adaptive spatial filtering is first described. The 0.18-mum CMOS fabricated sensor is then shown coupled to a microfluidic channel via a polymer encapsulated chip-on-board approach as well as a preferred flip-chip-on-glass hybrid integration approach. However, both approaches discussed possess attributes that are well suited for reliable high-volume production. Utilizing these two disparate assembly topologies, the intelligent sensor's general behavior, optical input dynamic range, and near-field sensitivity to polymer beads being transported in a microfluidic channel is explored. The findings suggest that discrete near-field sensor integration with microfluidics is a well-positioned integration approach for helping to obviate the need for precision analog-to-digital conversion, optical fiber microchannel coupling, and conventional microscopy for a set of relevant micro total analysis system applications. By opting instead for a hybrid multichip module approach to system integration, this study marks a slight departure in strategy relative to many common monolithic system-on-chip integration efforts View full abstract»

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  • CMOS-Based Phase Fluorometric Oxygen Sensor System

    Page(s): 111 - 118
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    The design and development of a phase fluorometric oxygen (O2 ) sensor system using single-chip CMOS detection and processing integrated circuit (DPIC) and sol-gel derived xerogel thin-film sensor elements is described. The sensor system determines analyte concentrations using the excited state lifetime measurements of an O2-sensitive luminophore (tris(4,7-diphenyl-1,10- phenathroline)ruthenium (II)) embedded in the xerogel matrix. A light emitting diode (LED) is used as the excitation source, and the fluorescence is detected by the DPIC using a 16times16 phototransistor array on-chip. The DPIC also consists of a current mirror, current-to-voltage converter, amplifier, bandpass filter, and phase detector. The DPIC output is a dc voltage that corresponds to the detected fluorescence phase shift. With a 14-kHz modulation frequency, the entire system including driving the LED consumes 80 mW of average power. The sensor system provides stable, reproducible, analytically reliable, and fast response (~20 s) to changes in the gaseous oxygen concentrations and establishes the viability for low cost, low power and miniaturized biochemical sensor systems View full abstract»

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  • A CMOS ISFET Interface Circuit With Dynamic Current Temperature Compensation Technique

    Page(s): 119 - 129
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    This paper presents a new ion-sensitive field-effect transistor (ISFET ) readout circuit including a novel nonlinear temperature compensation method that is based on the theoretical work for formulating a body-effect-based ISFET drain current expression, the derivation of an unified temperature-dependent ISFET threshold voltage expression, and the use of iterative method for solving design parameters in nonlinear equations. Regarding the basic readout circuit, it comprises only one source follower and one current source to establish a self-biased configuration for a single ISFET device. Due to elimination of body effect, it displays linear transfer characteristic in the experimental result. Incorporating temperature compensation further improves the thermal stability of the ISFET device in pH sensing function. This has been validated by the experimental results on pH values ranging from 4 to 9 in a temperature range of 22 degC to 50 degC from the measurement setup. The pH7 parameter is used as a reference in the method. The proposed works are attractive in terms of circuit simplicity, temperature-compensated performance, cost and compatibility for smart sensor operation View full abstract»

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  • Ultra-Low-Power Interface Chip for Autonomous Capacitive Sensor Systems

    Page(s): 130 - 140
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    Traditionally, most of the sensor interfaces must be tailored towards a specific application. This approach results in a high recurrent design cost and time to market. On the other hand, generic sensor interface design reduces the costs and offers a handy solution for multisensor applications. This paper presents a generic sensor interface chip (GSIC), which can read out a broad range of capacitive sensors. It contains capacitance-to-voltage converters, a switched-capacitor amplifier, an analog-to-digital converter, oscillators, clock generation circuits and a reference circuit. The system combines a very low-power design with a smart energy management, which adapts the current consumption according to the accuracy and speed requirements of the application. The GSIC is used in a pressure and an acceleration monitoring system. The pressure monitoring system achieves a current drain of 2.3 muA for a 10-Hz sample frequency and an 8-bit accuracy. In the acceleration monitoring system, we measured a current of 3.3 muA for a sample frequency of 10 Hz and an accuracy of 9 bits View full abstract»

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  • CMOS-Based Monolithic Controllers for Smart Sensors Comprising Micromembranes and Microcantilevers

    Page(s): 141 - 152
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    This paper presents design considerations and implementations of monolithic controllers for smart sensors that make use of micromachined structures such as micromembranes and microcantilevers. Five control techniques are reviewed, and the classic control technique is selected for the design of the controllers. The circuit implementations of an analog proportional controller and a digital proportional-integral-derivative controller are described in detail. The first controller is used for controlling the microhotplate (micromembrane) temperature of a monolithic metal-oxide gas sensor array. The second controller is used for controlling the microcantilever deflection of a monolithic atomic force microscope. The controllers and microsensors are fabricated in standard 0.8-mum CMOS technology combined with post-CMOS micromachining. Chemical measurements and contact-mode imaging are performed to confirm the excellent performance of these monolithic controllers View full abstract»

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  • Analysis and Design Strategy of UHF Micro-Power CMOS Rectifiers for Micro-Sensor and RFID Applications

    Page(s): 153 - 166
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    Design strategy and efficiency optimization of ultrahigh-frequency (UHF) micro-power rectifiers using diode-connected MOS transistors with very low threshold voltage is presented. The analysis takes into account the conduction angle, leakage current, and body effect in deriving the output voltage. Appropriate approximations allow analytical expressions for the output voltage, power consumption, and efficiency to be derived. A design procedure to maximize efficiency is presented. A superposition method is proposed to optimize the performance of multiple-output rectifiers. Constant-power scaling and area-efficient design are discussed. Using a 0.18-mum CMOS process with zero-threshold transistors, 900-MHz rectifiers with different conversion ratios were designed, and extensive HSPICE simulations show good agreement with the analysis. A 24-stage triple-output rectifier was designed and fabricated, and measurement results verified the validity of the analysis View full abstract»

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  • Highly Adaptive Transducer Interface Circuit for Multiparameter Microsystems

    Page(s): 167 - 178
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    A reconfigurable transducer interface circuit that combines the communication and signal conditioning necessary to link a variety of sensors and actuators to a microsystem controller is reported. The adaptive readout circuitry supports high-resolution signal acquisition from capacitive, resistive, voltage and current mode sensors with programmable control of gain and offset to match sensor range and sensitivity. The chip accommodates sensor self test and self calibration and supports several power management schemes. It provides digital and analog outputs to control actuators and a standard interface to peripheral components. The 2.2times2.2 mm CMOS chip was fabricated in 0.5-mum, 3-metal, 2-poly process, dissipates ~50 muW at 3.3 V in a typical multisensor application utilizing periodic sleep mode, and can read out a wide range of sensors with high sensitivity. A prototype microsystem with a microcontroller and MEMS pressure, humidity, and temperature sensors has been implemented to characterize interface chip performance View full abstract»

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  • Fully Integrated High-Voltage Front-End Interface for Ultrasonic Sensing Applications

    Page(s): 179 - 190
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    This paper concerns the design and implementation of a fully integrated high-voltage (HV) front-end transducer for ultrasonic sensing applications. This includes a programmable HV dc-dc converter (HVDC), a drive amplifier, and a tuneable pulse generator. The HVDC is based on a multistage two-phase voltage doubler and static level up shifters. The drive amplifier is composed of a static level-up stage and a Class-D switching output stage. Post-layout simulation and experimental silicon results are reported for two HVDC stages and a drive amplifier, which were fabricated using a 0.8-mum CMOS/DMOS process and having a supply voltage of 5 V/400 V. The measurement results confirm the validation of the HV circuit implementation and its design optimization. An output voltage of up to 200 V was obtained from the HVDC. Also, the drive amplifier generates spikes up to 148 V, with rise and fall times of 69 and 58 ns, respectively. The peak current flowing through the transducer element can be as high as 200 mA View full abstract»

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  • Editorial ISCAS 2006 Special Section on Analog Circuits and Systems

    Page(s): 191 - 192
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  • Switched-Capacitor Track-and-Hold Amplifiers With Low Sensitivity to Op-Amp Imperfections

    Page(s): 193 - 199
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    This paper describes high-precision switched-capacitor (SC) track-and-hold amplifier (THA) stages. They use a novel continuous-time correlated double sampling (CDS) scheme to desensitize the operation to amplifier imperfections. Unlike earlier predictive-CDS amplifiers, the circuits do not need a sampled-and-held input signal for their operation. During the tracking period, an auxiliary continuous-time signal path is established, which predicts the output voltage during the holding period. This allows accurate operation even for low amplifier gains and large offsets over a wide input frequency range. Extensive simulations were performed to compare the performance of the proposed THAs with earlier circuits utilizing CDS. The results verify that their operation is far more robust than that of any previously described SC amplifiers View full abstract»

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  • Design and Packaging of a Fully Autonomous Medical Monitoring System for Dental Applications

    Page(s): 200 - 208
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    In attempts to improve the quality of life (QOL), methods that make use of the symbiosis between medicine and technology are sought continuously. The insight in biomedical processes opens the way to a technically controlled rehabilitation. One such approach uses the know-how on bone remodeling and bone growth in a dental environment. By applying an immediate load on a newly placed implant, the bone growth is positively stimulated. However, excessive loading should be avoided at all times. Therefore, a fully implantable device was designed that is able to monitor the load continuously and provide feedback when overloading occurs. To the authors' knowledge, it is the first time such a system is proposed. In this paper, the design of the smart dental prosthesis is elaborated View full abstract»

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  • A Design-Optimized Continuous-Time Delta–Sigma ADC for WLAN Applications

    Page(s): 209 - 217
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    A third-order continuous-time delta-sigma (DeltaSigma) analog-to-digital converter (ADC) is presented for the conversion of an input signal bandwidth of 10 MHz. Design optimization towards minimal power consumption is demonstrated for the high-speed low-power building blocks of the DeltaSigma modulator. From this point of view, it is shown that GmC integrators are preferred over RC integrators in the low-pass filter of the modulator because they show a better tradeoff between power, speed, and accuracy. A new single-bit quantizer topology is presented that incorporates a local feedback path that improves stability using a switched-voltage technique. Finally, a design methodology for the single-bit digital-to-analog converter (DAC) in the feedback loop is proposed, focusing on the impact of high sampling rates on the stability of the converter. The presented continuous-time ADC achieves a simulated dynamic range of 72 dB and a signal-to-noise-and-distortion-ratio of 66 dB in a 10-MHz signal bandwidth. Therefore, it can be applied for WLAN broadband communication. The power consumption of the DeltaSigma modulator is limited to 7.5 mW. The chip is designed in a 0.18-mum triple-well CMOS technology View full abstract»

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  • Fast State-Space Harmonic-Distortion Estimation in Weakly Nonlinear Gm−C Filters

    Page(s): 218 - 228
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    A fast, one-pass harmonic-distortion estimation algorithm for G m-C filters is introduced. It is derived using state-space modeling and can be applied directly to Gm-C filters, of any order, with MOS transconductors exhibiting any type of weak nonlinearity. The algorithm is formed out of a small number of explicit expressions involving the filter's structural matrices and the transconductors' nonlinearity. It can be easily implemented in MATLAB. For verification of the theoretical development, the algorithm was used to derive the harmonic distortion of a single-ended Gm-C filter with weakly nonlinear transconductors designed on a 0.5-mum technology. The results of the algorithm and CADENCE simulation were found to be in good agreement View full abstract»

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  • On the Static Resolution of Digitally Corrected Analog-to-Digital and Digital-to-Analog Converters With Low-Precision Components

    Page(s): 229 - 237
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    This semi-tutorial paper considers the effect of component mismatch on the static accuracy of analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with digital correction. First, it is noted that the effective static resolution of flash ADCs is not much reduced by component mismatch: with proper digital correction, the loss due to mismatch is only about 1.3 bit, virtually independently of the mismatch level unless the mismatch is very small. Second, it is noted that current steering DACs may actually benefit from component mismatch. Moreover, with proper digital correction, current steering DACs can achieve an effective static resolution of m bits with as few as m+2 near-unit low-precision current sources View full abstract»

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Aims & Scope

The theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing.

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Meet Our Editors

Editor-in-Chief
Shanthi Pavan
Indian Institute of Technology, Madras