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IEEE Transactions on Computers

Issue 2 • Feb. 2007

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Displaying Results 1 - 19 of 19
  • [Front cover]

    Publication Year: 2007, Page(s): c1
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  • [Inside front cover]

    Publication Year: 2007, Page(s): c2
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  • Introduction to the Special Section on Nano Systems and Computing

    Publication Year: 2007, Page(s):145 - 146
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (98 KB) | HTML iconHTML

    The five papers in this special section cover a wide spectrum of techniques which are encountered in nano-scale computing systems. Briefly summarizes the articles included in this section. View full abstract»

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  • ZettaRAM: A Power-Scalable DRAM Alternative through Charge-Voltage Decoupling

    Publication Year: 2007, Page(s):147 - 160
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4037 KB) | HTML iconHTML

    ZettaRAMtrade is a nascent memory technology with roots in molecular electronics. It uses a conventional DRAM architecture except that the conventional capacitor is replaced with a new molecular capacitor. The molecular capacitor has a discrete threshold voltage, above which all molecules are charged and below which all molecules are discharged. Thus, while voltage still controls charging/discharg... View full abstract»

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  • Architecture of a Self-Checkpointing Microprocessor that Incorporates Nanomagnetic Devices

    Publication Year: 2007, Page(s):161 - 173
    Cited by:  Papers (7)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3517 KB) | HTML iconHTML

    Memory and latch circuits in CMOS systems rely on capacitatively-stored charge to hold state information. When power is removed from a chip, this charge quickly drains off, destroying any information that was contained in the chip. This causes a number of problems for computer systems, including data loss from power failures, the need to load operating systems from nonvolatile storage each time th... View full abstract»

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  • Hierarchical Probabilistic Macromodeling for QCA Circuits

    Publication Year: 2007, Page(s):174 - 190
    Cited by:  Papers (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (8878 KB) | HTML iconHTML

    With the goal of building an hierarchical design methodology for quantum-dot cellular automata (QCA) circuits, we put forward a novel, theoretically sound, method for abstracting the behavior of circuit components in QCA circuit, such as majority logic, lines, wire-taps, cross-overs, inverters, and corners, using macromodels. Recognizing that the basic operation of QCA is probabilistic in nature, ... View full abstract»

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  • Neural Network Simulation and Evolutionary Synthesis of QCA Circuits

    Publication Year: 2007, Page(s):191 - 201
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1481 KB) | HTML iconHTML

    CMOS technology miniaturization limits have promoted research on new alternatives which can keep the technologically advanced level of the last decades. Quantum-dot cellular automata (QCA) is a new technology in the nanometer scale that has been considered as one of these alternatives. QCA have a large potential in the development of circuits with high space density and low heat dissipation and al... View full abstract»

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  • Scaling and Better Approximating Quantum Fourier Transform by Higher Radices

    Publication Year: 2007, Page(s):202 - 207
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (385 KB) | HTML iconHTML

    Quantum Fourier transform (QFT) plays a principal role in the development of efficient quantum algorithms. Since the number of quantum bits that can be built is limited, while many quantum technologies are inherently three (or more) valued, we consider extending the reach of the realistic quantum systems by building a QFT over ternary quantum digits. Compared to traditional binary QFT, the q-value... View full abstract»

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  • Exploiting Operand Availability for Efficient Simultaneous Multithreading

    Publication Year: 2007, Page(s):208 - 223
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (4275 KB) | HTML iconHTML

    We propose several schemes to improve the scalability, reduce the complexity and delays, and increase the throughput of dynamic scheduling in SMT processors. Our first design is an adaptation of the proposed instruction packing to SMT. Instruction packing opportunistically packs two instructions (possibly from different threads), each with at most one nonready source operand at the time of dispatc... View full abstract»

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  • A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields

    Publication Year: 2007, Page(s):224 - 233
    Cited by:  Papers (59)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (435 KB) | HTML iconHTML

    Based on Toeplitz matrix-vector products and coordinate transformation techniques, we present a new scheme for subquadratic space complexity parallel multiplication in GF(2n) using the shifted polynomial basis. Both the space complexity and the asymptotic gate delay of the proposed multiplier are better than those of the best existing subquadratic space complexity parallel multipliers. ... View full abstract»

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  • Fast Multicomputation with Asynchronous Strategy

    Publication Year: 2007, Page(s):234 - 242
    Cited by:  Papers (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2358 KB) | HTML iconHTML

    We propose a new strategy to improve the performance of multicomputations, such as computing xA + yB in an additive group or a xby in a multiplicative group. This new strategy is called asynchronous strategy. In each iteration, it tries to compute partial results by pairing nearby zero and nonzero bits. The new strategy can be applied to any binary code of x and y to further ... View full abstract»

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  • Error Correction On-Demand: A Low Power Register Transfer Level Concurrent Error Correction Technique

    Publication Year: 2007, Page(s):243 - 252
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2482 KB) | HTML iconHTML

    Errors introduced by radiation-induced single event upset and single event latchup in very deep submicron (VDSM) ICs necessitate concurrent error detection (CED) and correction. Power consumed by circuits used for detecting and correcting errors becomes an extra burden on the tight power budget of VDSM ICs. The triple-modular redundancy-based fault tolerance technique, which is traditionally used ... View full abstract»

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  • Quality-of-Control Management in Overloaded Real-Time Systems

    Publication Year: 2007, Page(s):253 - 266
    Cited by:  Papers (28)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2127 KB) | HTML iconHTML

    Transient overload conditions may cause unpredictable performance degradations in computer controlled systems if not properly handled. To prevent such problems, a common technique adopted in periodic task systems is to reduce the workload by enlarging activation periods. In a digital controller, however, the variation applied on the task period also affects the control law, which needs to be recom... View full abstract»

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  • The Design of New Journaling File Systems: The DualFS Case

    Publication Year: 2007, Page(s):267 - 281
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2716 KB) | HTML iconHTML

    This paper describes the foundation, design, implementation, and evaluation of DualFS, a new high-performance journaling file system which has the same consistency guarantees as traditional journaling file systems but a greater performance. DualFS places data and metadata in different devices (usually, two partitions of the same storage device) and manages them in very different ways. The metadata... View full abstract»

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  • A New Systolic Architecture for Modular Division

    Publication Year: 2007, Page(s):282 - 286
    Cited by:  Papers (6)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2061 KB) | HTML iconHTML

    A new systolic architecture for modular division is proposed in this paper. The architecture is based on a new hardware algorithm for modular division that is extended from the plus-minus algorithm for the greatest common divisor computation. Both the area complexity and the time complexity of the new architecture are linear with respect to the operand bit length. Compared to the architecture usin... View full abstract»

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  • In this issue

    Publication Year: 2007, Page(s): 287
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  • IEEE Computer Society Digital Library [advertisement]

    Publication Year: 2007, Page(s): 288
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  • TC Information for authors

    Publication Year: 2007, Page(s): c3
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  • [Back cover]

    Publication Year: 2007, Page(s): c4
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Aims & Scope

The IEEE Transactions on Computers is a monthly publication with a wide distribution to researchers, developers, technical managers, and educators in the computer field.

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Meet Our Editors

Editor-in-Chief
Paolo Montuschi
Politecnico di Torino
Dipartimento di Automatica e Informatica
Corso Duca degli Abruzzi 24 
10129 Torino - Italy
e-mail: pmo@computer.org