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IEEE Design & Test of Computers

Issue 3 • Sept. 1992

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Displaying Results 1 - 7 of 7
  • DAG-Map: graph-based FPGA technology mapping for delay optimization

    Publication Year: 1992, Page(s):7 - 20
    Cited by:  Papers (57)  |  Patents (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1221 KB)

    A graph-based technology-mapping package for delay optimization in lookup-table-based field programmable gate array (FPGA) designs is presented. The algorithm, DAG-Map, carries out technology mapping and delay optimization on the entire Boolean network, instead of decomposing it into fan-out-free trees. As a preprocessing phase of DAG-Map, a general algorithm called DMIG, which transforms an arbit... View full abstract»

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  • AnyBoard: an FPGA-based, reconfigurable system

    Publication Year: 1992, Page(s):21 - 30
    Cited by:  Papers (31)  |  Patents (14)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (973 KB)

    AnyBoard, a low-cost, field programmable gate array (FPGA)-based, reconfigurable rapid-prototyping system is described. The system hardware organization and software tools that help users automatically map designs to the FPGAs and manage the design process are discussed. The implementation of a pattern generator design is presented to illustrate the system's effectiveness.<> View full abstract»

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  • Using VHDL for high-level, mixed-mode system simulation

    Publication Year: 1992, Page(s):31 - 40
    Cited by:  Papers (10)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1106 KB)

    The application of a very-high-speed integrated circuit hardware description language (VHDL) to the modeling of complex, application-specific systems that employ a mix of digital hardware and software and interact with their environments through continuous-time components is described. A VHDL model simulating package and a SPICE-like low-level package simulating continuous-time subsystems are disc... View full abstract»

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  • Optimizing VHDL compilation for parallel simulation

    Publication Year: 1992, Page(s):42 - 53
    Cited by:  Papers (4)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1399 KB)

    Auriga, an experimental simulator that utilizes five compilation techniques to reduce runtime complexity and promote concurrency in the simulation of VHDL models is described. Auriga is designed to translate a model using any VHDL construct into an optimized, parallel simulation. Auriga's distributed simulation uses a message-passing network to simulate a single VHDL model. The authors present res... View full abstract»

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  • Three decades of HDLs. II. Conlan through Verilog

    Publication Year: 1992, Page(s):54 - 63
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1007 KB)

    For pt.1 see ibid., June 1992. Current hardware description languages (HDLs) benefit from the efforts of designers of VHDLs in the mid-1970s through the late 1980s. The developers of four HDLs discuss their motivations and their views of how their work relates to the present very-high-speed integrated circuit HDLs (VHDLs). The languages discussed are Conlan, ADLIB/SABLE, Zeus, and Verilog.<> View full abstract»

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  • Applying testability analysis for integrated diagnostics

    Publication Year: 1992, Page(s):65 - 78
    Cited by:  Papers (10)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1322 KB)

    The use of measures that evaluate system testability at a specific time during system design is demonstrated. The measures were detailed in a previous article (see ibid., vol.9, no.1, p.40-54 (1992)). The measures improve testability as part of an interactive process. The objective in applying the testability measures is to minimize ambiguity in replaceable unit groups while minimizing the amount ... View full abstract»

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  • Boundary-scan update-IEEE P1149.2 description and status report

    Publication Year: 1992, Page(s):79 - 81
    Cited by:  Papers (2)  |  Patents (5)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (192 KB)

    The IEEE P1149.2 Working Group is developing a standard that supports boundary scan for board-level interconnect testing and supports internal scan for device- or board-level component testing. The group's overall objective is to establish minimal mandatory features that are adaptable to individual applications. P1149.2's current status and the most recent proposals being considered for the standa... View full abstract»

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This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Krishnendu Chakrabarty