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Electron Device Letters, IEEE

Issue 1 • Date Jan. 2007

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Displaying Results 1 - 25 of 31
  • Table of contents

    Publication Year: 2007 , Page(s): C1 - C4
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  • IEEE Electron Device Letters publication information

    Publication Year: 2007 , Page(s): C2
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  • What is in a page charge?

    Publication Year: 2007 , Page(s): 1
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  • RF-Enhanced Contacts to Wide-Bandgap Devices

    Publication Year: 2007 , Page(s): 2 - 4
    Cited by:  Papers (2)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (177 KB) |  | HTML iconHTML  

    This letter proposes a novel approach to fabricate high-performance heterostructure microwave devices with nonohmic contacts. The contact can be as-deposited or made by "shallow" low-temperature annealing to form a low-height Schottky barrier while preserving the two-dimensional electron-gas layer (2DEG) at the heterointerface. Coupling between the metal and the 2DEG occurs via two paths: dc current injects through the barrier leakage current and ac-current component injects through capacitive coupling. Contacts with resistive/capacitive coupling have low microwave impedance and enhance the heterostructure field-effect transistor's maximum oscillation frequency, output power, and power-added efficiency as compared to resistive ohmic contacts View full abstract»

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  • Power Stability of AlGaN/GaN HFETs at 20 W/mm in the Pinched-Off Operation Mode

    Publication Year: 2007 , Page(s): 5 - 7
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (95 KB) |  | HTML iconHTML  

    High power-added efficiency (PAE) (ap74%) and rf-power (20 W/mm) operation of Schottky and insulated-gate AlGaN/GaN heterostructure field-effect transistors (HFETs) is reported at 2 GHz. In the pinched-off mode of operation, the PAE increases from a value of 55% to 74% when the drain bias is changed from 35 to 60 V. While both the Schottky and the insulated HFETs show high powers and PAE values, only the insulated-gate devices are stable at 20-W/mm output powers during a 60-h continuous wave rf-stress test. Their power drop of less than 0.1 dB is much smaller than the 0.8-dB drop for identical geometry Schottky-gate HFETs. The superior stability of the insulated-gate HFETs is attributed to the low forward gate currents View full abstract»

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  • DC Characteristics of AlGaAs/GaAs/GaN HBTs Formed by Direct Wafer Fusion

    Publication Year: 2007 , Page(s): 8 - 10
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (99 KB) |  | HTML iconHTML  

    We have fabricated AlGaAs/GaAs/GaN heterojunction bipolar transistors (HBTs) formed by direct wafer fusion with different fusion temperatures. By employing a low wafer fusion temperature of 550 degC, current gains as high as ~9 and output currents as high as ~65 mA (emitter size of 100times120 mum2) were obtained. The effective minority carrier lifetime in the base was estimated to have decreased ~20 times due to the fusion process. In comparison, HBTs produced with higher wafer fusion temperatures (600 degC and 650 degC) exhibit lower current gains (~2-3) and higher base-collector leakage currents View full abstract»

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  • Impacts of Dopant Segregation on the Performance and Interface-State Density of the MOSFET With FUSI NiSi Gate

    Publication Year: 2007 , Page(s): 11 - 13
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (466 KB) |  | HTML iconHTML  

    MOSFET characteristics of NiSi fully silicidation of polysilicon gates are found to be influenced by preimplanted dopant. Dopant segregation induced by silicidation at gate/oxide interface is observed to affect threshold voltage, subthreshold swing, effective mobility, and interface characteristics. The degradation of MOSFET characteristics in B-doped NiSi metal gate is found to be related to increasing interface-state density due to silicidation-induced impurity segregation View full abstract»

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  • Resistive Switching Mechanism in ZnxCd1 − xS Nonvolatile Memory Devices

    Publication Year: 2007 , Page(s): 14 - 16
    Cited by:  Papers (6)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (118 KB) |  | HTML iconHTML  

    Nonvolatile information storage devices based on an abrupt resistance switch when an electric bias is applied are very attractive for future memory applications. Recently, such a resistance switch was described in ferroelectric ZnxCd1-xS, but the mechanism of switching remains controversial. Here, we present results that elucidate the mechanism, showing that a metal needs to be easily oxidized and is capable of diffusing into the ZnCdS film as a cation impurity forming a filamentary metallic conduction path View full abstract»

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  • High-Performance Metal–Insulator–Metal Capacitors Using Amorphous BaSm2Ti4O12 Thin Film

    Publication Year: 2007 , Page(s): 17 - 20
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (140 KB) |  | HTML iconHTML  

    The dielectric properties of the amorphous BaSm2Ti4O12 (BSmT) film with various thicknesses were investigated to evaluate its potential use as a metal-insulator-metal (MIM) capacitor. An amorphous 35-nm-thick BSmT film grown at 300 degC exhibited a high capacitance density of 9.9 fF/mum2 at 100 kHz and a low leakage current density of 1.790 nA/cm2 at 1 V. The quadratic and linear voltage coefficients of capacitance of the film were 599 ppm/V2 and -81 ppm/V at 100 kHz, respectively. The temperature coefficient of capacitance of the film was also low about 236 ppm/degC at 100 kHz. These results confirmed the suitability of the amorphous BSmT film as a high-performance MIM capacitor View full abstract»

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  • Effect of F2 Postmetallization Annealing on the Electrical and Reliability Characteristics of HfSiO Gate Dielectric

    Publication Year: 2007 , Page(s): 21 - 23
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (412 KB) |  | HTML iconHTML  

    The effects of fluorine (F2) annealing on the electrical and reliability characteristics of HfSiO MOSFETs were investigated. Compared with a control sample annealed in conventional forming gas (H2/N2=4%/96%), additional annealing in a fluorine ambient (F2/Ar=0.3%/99.7%) at 400 degC for 20 min improved the electrical characteristics such as lower interface trap density and higher transconductance. In addition, MOSFET samples annealed in a F2 ambient exhibited less degradation under hot-carrier stress and positive bias temperature stress. These improvements can be explained by fluorine incorporation at the high-k/Si interface, which was confirmed by an X-ray photoelectron spectroscopy analysis View full abstract»

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  • High-κ Al2O3−HfTiO Nanolaminates With Less Than 0.8-nm Equivalent Oxide Thickness

    Publication Year: 2007 , Page(s): 24 - 26
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (123 KB) |  | HTML iconHTML  

    High quality nanolaminate stacks consisting of five Al2O3-HfTiO layers with an effective dielectric constant of about 22.5 are reported. A dielectric constant for binary HfTiO thick films of about 83 was also demonstrated. The electrical characteristics of as-deposited structures and ones which were annealed in an O2 atmosphere at up to 950 degC for 5-10 min were investigated. Two types of gate electrodes: Pt and Ti were compared. The dielectric stack which was annealed up to 500 degC exhibits a leakage current density as small as ~1times10-4 A/cm2 at an electric of field 1.5 MV/cm for a quantum-mechanical corrected equivalent oxide thickness of ~0.76 nm. These values change to ~1times10-8 A/cm2 and 1.82 nm, respectively, after annealing at 950 degC View full abstract»

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  • High-Quality Factor Electrolyte Insulator Silicon Capacitor for Wireless Chemical Sensing

    Publication Year: 2007 , Page(s): 27 - 29
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (196 KB) |  | HTML iconHTML  

    This letter reports on the design, fabrication, and characterization of a high Q electrolyte insulator silicon (EIS) capacitive structure and its application to LC wireless chemical sensors. LC sensors are based on the variation of inductance or capacitance in response to changes in the magnitude of interest. In this new type of LC sensor, the EIS structure is used as a pH-to-capacitance transductor. A double electrode scheme, one for stable dc potential and another for low ac series resistance, has been adopted in order to obtain sufficient Q at the resonator. An almost linear response and a sensitivity of 1% frequency change per pH unit have been achieved View full abstract»

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  • Robust Coupled-Quantum-Well Structure for Use in Electrorefraction Modulators

    Publication Year: 2007 , Page(s): 30 - 32
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (101 KB) |  | HTML iconHTML  

    In this letter, an InGaAs/InAlAs coupled-quantum-well structure that is very robust to layer thickness and the compositional variations is reported. The robustness occurs because the structure's electrorefraction (ER) is based on the anticrossing of the two lowest energy light-hole wave functions. The structure is, thus, more appropriate for use in transverse magnetic modulators rather than in transverse electric modulators. The robustness of the structure is shown to be superior to that of a similar structure that has its ER effect based on the anticrossing of the two lowest energy electron wave functions View full abstract»

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  • On-Pixel Voltage-Controlled Oscillator in Amorphous-Silicon Technology for Digital Imaging Applications

    Publication Year: 2007 , Page(s): 33 - 35
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (219 KB) |  | HTML iconHTML  

    The design and implementation of an on-pixel voltage-controlled oscillator for digital imaging applications based on a ring-oscillator circuit fabricated in amorphous silicon thin-film transistor technology is presented. Preliminary results on sensitivity, voltage to frequency gain, linearity, and simulation results of long-term stability appear promising for its application in large-area digital medical X-ray imagers View full abstract»

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  • Low-Frequency Noise Characteristics in Strained-Si nMOSFETs

    Publication Year: 2007 , Page(s): 36 - 38
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (184 KB) |  | HTML iconHTML  

    The low-frequency (LF) (1/f) noise mechanism of strained-Si nMOSFETs grown on relaxed Si1-xGex virtual substrates (VSs) has been investigated. It is found that the Si-cap thickness plays an important role in characterizing the 1/f noise mechanism. Ge out-diffusion effect and slight strain relaxation in Si-cap layer are responsible for the degradation of 1/f noise in strained-Si device with 10- and 20-nm-thick Si-cap, respectively. In addition, by choosing proper Si-cap thickness, experimental result shows that as Si-cap undergoes stronger tensile strain for higher Ge concentration VS, the correlated mobility fluctuation term in the modified carrier-number fluctuation model is more dominated for the 1/f noise View full abstract»

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  • A Novel Four-Mask-Step Low-Temperature Polysilicon Thin-Film Transistor With Self-Aligned Raised Source/Drain (SARSD)

    Publication Year: 2007 , Page(s): 39 - 41
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (370 KB) |  | HTML iconHTML  

    In this letter, a novel structure of polycrystalline-silicon thin-film transistors (TFTs) with self-aligned raised source/drain (SARSD) and a thin channel has been developed and investigated. In the proposed structure, a thick SD and a thin active region could be achieved with only four mask steps, which are less than that in conventional raised SD TFTs. The proposed SARSD TFT has a higher on-state current and a lower off-state leakage current. Moreover, the on/off current ratio of the proposed SARSD TFT is also higher than that of a conventional coplanar TFT View full abstract»

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  • HgTe Nanocrystal-Based Thin-Film Transistors Fabricated on Glass Substrates

    Publication Year: 2007 , Page(s): 42 - 44
    Cited by:  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (252 KB) |  | HTML iconHTML  

    HgTe nanocrystal-based thin-film transistors (TFTs) with Al2 O3 top-gate dielectrics were fabricated on glass substrates using sintered HgTe nanocrystals as the channel layers. To the best of our knowledge, this is the first report on the fabrication of nanocrystal-based TFTs on glass substrates. Colloidal HgTe nanocrystal films were first formed on the glass substrates by spin-coating. The HgTe nanocrystal films were then sintered at 150 degC, leading to a dramatic increase in their conductance, compared with the as-deposited films. The TFTs fabricated in this letter exhibit the typical characteristics of p-channel transistors with a field-effect mobility of 1.04 cm2/Vmiddots, a threshold voltage of +0.2 V, and an on/off current ratio of 1times103. These results suggest that spin-coating and sintering at a low temperature enable the simple and low-cost fabrication of nanocrystal-based TFTs on glass substrates View full abstract»

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  • Evaluation of RF Capacitance Extraction for Ultrathin Ultraleaky SOI MOS Devices

    Publication Year: 2007 , Page(s): 45 - 47
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (219 KB) |  | HTML iconHTML  

    This letter evaluates a radio-frequency (RF) method to extract the gate capacitance for SOI MOSFETs with ultrathin ultraleaky gate dielectrics. Conventional methods such as two-element and three-element methods using precision impedance analyzer were also compared. The RF method scans the RF capacitance data, assesses its lower and upper limits, and extracts the SOI gate capacitance accurately independent of gate oxide thickness View full abstract»

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  • Long Retention of Gain-Cell Dynamic Random Access Memory With Undoped Memory Node

    Publication Year: 2007 , Page(s): 48 - 50
    Cited by:  Papers (1)  |  Patents (61)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (437 KB) |  | HTML iconHTML  

    Low current leakage characteristics of a novel silicon-on-insulator (SOI) device are investigated in view of application to a gain-cell dynamic random access memory (DRAM). The device consists of a two-layered poly-Si gate. Since, in this device, the memory node is electrically formed by the gate in undoped SOI wire, no p-n junction is required. The retention is found to be dominated by the subthreshold leakage, which leads to long data retention. The device also achieved a fast (10 ns) writing time and its fabrication process is compatible with those of SOI MOSFETs. The present results, thus, strongly suggest a way of conducting a gain-cell DRAM to be embedded into logic circuits View full abstract»

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  • Time-Domain-Reflectometry for Capacitance–Voltage Measurement With Very High Leakage Current

    Publication Year: 2007 , Page(s): 51 - 53
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    Accurate capacitance-voltage (C-V) measurement of MOS capacitor with very high leakage current is a problem that does not yet has a satisfactory solution. Elaborated methods can improve the accuracy but increase the measurement complexity at the same time. Here, we introduce a novel new method to measure C-V under high leakage condition based on time-domain-reflectometry. This method is simple to use and offers high accuracy View full abstract»

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  • Threshold Current for the Onset of Kirk Effect in Bipolar Transistors With a Fully Depleted Nonuniformly Doped Collector

    Publication Year: 2007 , Page(s): 54 - 57
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (95 KB) |  | HTML iconHTML  

    We derive a generalized expression for the threshold current of the Kirk effect (base widening) in bipolar transistors that have a fully depleted collector and a nonuniform dopant distribution in the collector. This generalized expression can be helpful to the analysis of the electrical characteristics, such as the cutoff frequency as a function of bias conditions, and hence to the optimization of such devices View full abstract»

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  • Piezoresistance Coefficients of (100) Silicon nMOSFETs Measured at Low and High ( ∼ 1.5 GPa) Channel Stress

    Publication Year: 2007 , Page(s): 58 - 61
    Cited by:  Papers (15)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (288 KB) |  | HTML iconHTML  

    A flexure-based four-point mechanical wafer bending setup is used to apply large uniaxial tensile stress (up to 1.2 GPa) on industrial nMOSFETs with 0 to ~700 MPa of process-induced stress. This provides the highest uniaxial channel stress to date at ~1.5 GPa. The stress altered drain-current is measured for long and short (50-140 nm) devices and the extracted pi-coefficients are observed to be approximately constant for stresses up to ~1.5 GPa. For short devices, this trend is seen only after correcting for the significant degradation in the pi-coefficients observed due to parasitic source/drain series resistances (Rsd/) View full abstract»

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  • Electrical Characterization of ZrO2/Si Interface Properties in MOSFETs With ZrO2 Gate Dielectrics

    Publication Year: 2007 , Page(s): 62 - 64
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (289 KB) |  | HTML iconHTML  

    MOSFETs incorporating ZrO2 gate dielectrics were fabricated. The IDS-VDS, IDS-VGS , and gated diode characteristics were analyzed to investigate the ZrO2/Si interface properties. The interface trap density (D it) was determined to be about 7.4times1012 cm -2middoteV-1 using subthreshold swing measurement. The surface-recombination velocity (s0) and the minority carrier lifetime in the field-induced depletion region (tau 0,FIJ) measured from the gated diodes were about 3.5times10 3 cm/s and 2.6times10-6 s, respectively. The effective capture cross section of surface state (sigmas) was determined to be about 5.8times10-16 cm2 using the gated diode technique and the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO2 gate oxides was also made View full abstract»

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  • Improved Reliability by Reduction of Hot-Electron Damage in the Vertical Impact-Ionization MOSFET (I-MOS)

    Publication Year: 2007 , Page(s): 65 - 67
    Cited by:  Papers (23)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (151 KB) |  | HTML iconHTML  

    This letter presents experimental results and explanations on the reduced degradation caused by hot carriers of the vertical impact-ionization MOSFET (I-MOS) compared to the lateral device. The control and reduction of hot-carrier damage in an impact-ionization device is an important issue to make it a serious alternative for the conventional MOSFET to overcome the kT/q limit for the subthreshold slope of 60 mV/dec at room temperature. The vertical I-MOS shows an excellent subthreshold slope of about 13 mV/dec combined with a suppression of hot-carrier damage for the most part for many tens of thousands of switching cycles. We will explain the effects, which lead to this stability and validate it by measurements and simulations View full abstract»

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  • Bond Pad Design With Low Capacitance in CMOS Technology for RF Applications

    Publication Year: 2007 , Page(s): 68 - 70
    Cited by:  Papers (1)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (255 KB) |  | HTML iconHTML  

    A new bond pad structure in CMOS technology with low capacitance for gigahertz radio frequency applications is proposed. Three kinds of inductors stacked under the pad are used in the proposed bond pad structure. Experimental results have verified that the bond pad capacitance is reduced due to the cancellation effect provided by the inductor embedded in the proposed bond pad structure. The new proposed bond pad structure is fully process-compatible to general CMOS processes without any extra process modification View full abstract»

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IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron devices.

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Amitava Chatterjee