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Electronic Computers, IEEE Transactions on

Issue 5 • Date Oct. 1967

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Displaying Results 1 - 25 of 47
  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Group

    Page(s): nil1
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    Freely Available from IEEE
  • [Breaker page]

    Page(s): nil1
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    Freely Available from IEEE
  • Editor's Notice

    Page(s): 549
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    Freely Available from IEEE
  • Foreword to Special Issue on Aerospace Computers

    Page(s): 550
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    Freely Available from IEEE
  • Design Considerations for a Parallel Bit-Organized MOS Memory

    Page(s): 551 - 557
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    This paper discusses the design trade-offs for a parallel bit-organized MOS memory. A memory capacity of 40K bits can be achieved using LSI techniques. Memory storage capacity is expandable in both word length and number of words stored. The physical dimensions of the memory should be considerably smaller than those of a comparable core design. Power consumption per bit should likewise be less than that achievable with cores. A full cycle time of 1 us or less can be achieved. Cost per bit should compare very favorably with that of a core design. View full abstract»

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  • Impact of Large Scale Integration on Aerospace Computers

    Page(s): 558 - 561
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    The continued development of Large Scale Integration (LSI) presages the advent of a fourth generation of computers, and is causing an upheaval at all levels of computer technology¿both technical and managerial. Today's computers use integrated circuit components containing at most ten gates per component; however, LSI is introducing hundreds of gates per component and will eventually evolve into thousands of gates per component. To the aerospace planner, this technological breakthrough of LSI means tremendous reductions in cost, size, weight, and power consumption of logic components, together with increased speed and reliability. However, for the aerospace planner to successfully implement aerospace computers with LSI, the computer designers and managers must reorient their methodology and goals. A multitude of new design and cost considerations must be carefully scrutinized, and out of this must come the new techniques that will permit effective incorporation of LSI in aerospace computers. Higher speed, a smaller system, greater reliability, and lower cost stem from the physical structure (more gates per component with no increase in component size) of the LSI component. These inherent features of LSI, together with multiprocessor system organization, point to future aerospace computers with capabilities equal to today's best ground base systems. View full abstract»

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  • System Utilization of Large-Scale Integration

    Page(s): 562 - 566
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    A new approach to a computer organization promises very effective utilization of the LSI technology. Functional partitioning of both the data path and control is employed. A dramatic reduction in array pin requirements by a factor of two or more is achieved. Arrays as small as a few dozen gates can be effectively utilized. The total system is exceedingly flexible in both performance and instruction set. View full abstract»

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  • Programmed Algorithms to Compute Tests to Detect and Distinguish Between Failures in Logic Circuits

    Page(s): 567 - 580
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    Two algorithms are presented: one, DALG-II, computes a test to detect a failure in acyclic logic circuits; the other, TEST-DETECT, ascertains all failures detected by a given test. Both are based upon the utilization of a ``calculus of D-cubes'' that provides the means for effectively performing the necessary computations for very large logic circuits. Strategies for combining the two algorithms into an efficient diagnostic test generation procedure are given. APL specifications of the algorithms are given in an Appendix. View full abstract»

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  • Automatic Checkout Systems for Titan III and Apollo Guidance Computer Programs

    Page(s): 580 - 590
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    The Automatic Checkout Systems (ACS) were designed and used for the Titan III and Apollo Projects. This article describes the logical design of new approaches to program checkout and the results achieved. These checkout systems are a series of programs written for a large scale commercial computer. When a program for the airborne computer of the inertial guidance system is operated on by the ACS, it performs a symbolic simulation and generates the symbolic equations (A=B+C×D) that are performed by the airborne computer program. The ACS performs many checks for program errors in this process, indicates all areas where program analysis is required, and furnishes the program information required for analysis in optimum form. The equations generated by the ACS are manually checked against the input specification. This check is absolute in nature compared to the conventional method of analyzing the results of numerical simulations. Time consumed on the large scale commercial computer is much less than for numerical simulation. View full abstract»

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  • Redundant System Test Point Allocation and Mission Reliability Estimation Procedures

    Page(s): 591 - 596
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    The steadily increasing complexity of spaceborne digital systems tends to lower the reliability of these systems that operate in an environment where the cost of failure is extremely high. The reliability of digital systems can be increased by redundancy techniques. The majority of work in redundancy has concentrated on the development of synthesis techniques and initial reliability estimation procedures. Relatively little effort has been spent on the development of procedures for testing redundant systems and estimating their reliability when some components may be failed. This paper describes 1) a procedure for allocating a limited number of test points within a redundant digital system, and 2) a compatible procedure for estimating the probability of successfully completing a mission, using information obtained from the allotted test points. View full abstract»

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  • Reliability Aspects of the Variable Instruction Computer

    Page(s): 596 - 602
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    This paper is intended to show how the unique features of the Variable Instruction Computer (VIC) make it valuable for applications requiring high reliability. By careful choice of components, use of error-checking circuits, and selected application of redundant hardware, the basic unextended reliability of the VIC is comparable with the state-of-the-art. This is verified by a standard MIL-HDBK-217 type of analysis. The variable instruction technique is briefly described by use of a block diagram. The method for extending reliability by use of variable instructions is explained and an example is given. The concept of algorithm change to achieve controlled graceful degradation is discussed. An analysis of a typical application of this technique is given and extensions of the variable instruction concept to more advanced reliability requirements are discussed. View full abstract»

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  • Monte Carlo Solution of Partial Differential Equations Using a Hybrid Computer

    Page(s): 603 - 610
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    The analog-hybrid computer Monte Carlo technique for solving elliptic and parabolic partial differential equations has been implemented on a new hybrid computer capable of taking statistics over 1000 two-or three-dimensional random walks per second. This exceptional computing speed and flexible digital control permit direct plotting of partial differential equation solutions; of perhaps even greater interest is the incorporation of such Monte Carlo routines in real-time analog computer setups in process control applications. In this connection, the Monte Carlo method has been extended to a wider class of problems, and is especially applicable to heat conduction/diffusion problems. View full abstract»

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  • Partitioned List Algorithms for Prime Implicant Determination from Canonical Forms

    Page(s): 611 - 620
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    The structure of the algorithms implementing Quine's method for prime implicant determination is analyzed, and a new class of algorithms¿partitioned list algorithms¿for Quine's method is derived. Such algorithms are of particular interest for actual computation because they permit 1) avoiding repetitions while generating clauses, 2) representing each clause by only one binary configuration, 3) reducing memory capacity requirements, and 4) applying the basic operations by means of nonexhaustive techniques. View full abstract»

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  • A Correspondence Between Equivalence Classes of Switching Functions and Group Codes

    Page(s): 621 - 624
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    The correspondence defined below was used to convert Slepian's tabulation of the number of equivalence classes of (m, r) group codes[1] into hitherto unpublished data of relevance to switching theory. Specifically, Table II lists the number of equivalence classes of switching functions of weight m≪ 20 or m≫ 2n-20 in nine or fewer arguments under the group of linear transformations on its argument variables. The correspondence is established by means of an m×n binary matrix, all of whose rows are distinct. The rows of this matrix define m points at which a switching function of n arguments takes on unit value. If the rank of this matrix (over the 2-element field) is r, then its columns generate an r-dimensional subspace of binary m-tuples which, by definition, is the message set of an (m, r) group code. View full abstract»

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  • Symmetric Ternary Switching Functions: Their Detection and Realization with Threshold Logic

    Page(s): 624 - 637
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    A simple, systematic procedure for detecting symmetric ternary switching functions is developed. The detection procedure is essentially based on a derived counting theorem. Other important properties and close bounds on the number of ternary symmetric functions are developed. A design method is given whereby symmetric functions can be readily synthesized with switching networks which are economical, and, in certain instances, minimal in the number of ternary threshold devices required. The greatest lower bound on the number of devices required for a given symmetric function is developed. View full abstract»

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  • On the Synthesis of Signal Switching Networks with Transient Blocking

    Page(s): 637 - 641
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    Signal switching networks with transient blocking are defined. The number of 2×2 crossbars necessary to synthesize a signal switching network with transient blocking capable of performing all one-to-one connections of N inputs to N outputs is shown to be at least N log2N-N log2 e+(¿) log2 N + log2 2 + 0(1) as N¿ ¿. It is shown that this lower bound can never be attained for N ≫ 2. An algorithm for building a network using at most 2N log2 N 2×2 crossbars is described. If N is a power of 2, N = 2m, then the algorithm described requires N log2 N-N+1 2×2 crossbars, which is close to the theoretical minimum. Generalizations of this work to networks performing an arbitrary permutation group of connections of inputs to outputs are indicated. Explicit results are obtained in the case of Abelian groups. View full abstract»

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  • Plated Wire Content-Addressable Memories with Bit-Steering Technique

    Page(s): 642 - 652
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    This report describes a new concept of content-addressable memory (CAM) implemented with plated wires and the bit-steering technique. The 5-mil plated wires are insulated with a thin (0.2 to 0.3 mil) coat of polyurethane, and imbedded in a copper plane. A memory array is formed by means of a simple orthogonal arrangement of plated wires and an overlay of copper straps. Because of the low loop impedance (2 to 5 ohms depending on the design but uniform to within ± 5 percent for a given design) formed between an insulated plated wire and the copper plane, a loop current of the order of 30 mA can be generated by pulsing a pair of straps. This current is used to transfer information from one bit position to another bit along the same plated wire. Consequently, logic manipulations can be performed within the memory array. The resolve operation is executed in the array where a binary address tree is stored. The addresses of matched words are obtained via the sieving action of the tree. With a complementary address tree added to this resolve area, the addressed READ/WRITE operations are executed by first searching for the given address and then READ/WRITE on the matched word. The search cycle time of a CAM of 4096 words, 40 bits per word, is estimated to be about 1 to 2 ¿s, based upon experimental results. The resolve time is about 1.5 ¿s for any one of the 4096 addresses. View full abstract»

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  • Microprogrammed Control in Problem-Oriented Languages

    Page(s): 652 - 658
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    The application of microprogramming to problem-oriented languages is described in terms of a simulated analog system on a digital computer. Microprogramming facilitates the development of a problem-oriented machine code, which can be simply generated from the problem-oriented source language by simple translation. In the system described a problem defined by differential equations is drawn up in the form of an analog diagram. The diagram is coded into an analog-oriented source language which is converted by translation into the analog machine code. The system also allows the machine assembly code to be freely used with the analog input in coding the supervisory and interrupt facilities that are incorporated in the overall system design. View full abstract»

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  • Memory Allocation for Multiprocessors

    Page(s): 659 - 665
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    In multiprocessor systems it is desirable to look for and allocate storage without extensive data moving. Two techniques for accomplishing this, associative memory techniques and indirect addressing techniques, are described. It is concluded that the two methods are similar in performance, but that indirect addressing is more economical. An indirect addressing method is described in detail and various methods of implementation compared. The memory overhead and the time penalty (in memory accesses) are given as a function of memory size and method of implementation. It is concluded that a computed address table look-up technique should be used and that the block size should be either 256 or 512 words. View full abstract»

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  • Hybrid Computer Solution of Optimal Control Problems by the Maximum Principle

    Page(s): 666 - 670
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    When the maximum principle is applied to optimal control problems, a two-point boundary value problem must by necessity be solved. This paper discusses a solution method for general problems in which the initial and terminal states of the system are given, but in which the time of arrival at the terminal state is unknown. Various difficulties accompanying the conventional methods used in the past are pointed out, and a new method for solving these difficulties is proposed. The hybrid computing system is suitable for carrying out this method, and hybrid computers have been applied to the solution of numerous concrete problems. As a result, it becomes possible to seek a solution completely automatically, and it has been proven that this method is extremely practical. View full abstract»

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  • Graphs of Linear Forms on Modules over Boolean Rings

    Page(s): 670 - 671
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    This note considers the graphs of linear and affine transformations on modules over Boolean rings. It will be shown that such graphs are similar to those of linear forms on vector spaces over finite fields. View full abstract»

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  • On Minimal Modulo 2 Sums of Products for Switching Functions

    Page(s): 671 - 674
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    The minimal number of terms required for representing any switching function as a modulo 2 sums of products is investigated, and an algorithm for obtaining economical realization is described. The main result is the following: every symmetric function of 2m+1 variables has a modulo 2 sum of products realization with at most 3m terms; but there are functions of n variables which require at least 2n/n log2 3 terms for sufficiently large n. View full abstract»

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  • On Finding a Minimal Set of Diagnostic Tests

    Page(s): 674 - 675
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    A method is described for constructing a set of input patterns able to detect every given failure of a combinational network. The result may not be a minimal set of tests, but it is surely a complete test. View full abstract»

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  • Diagnosis of Large Combinational Networks

    Page(s): 675 - 680
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    A method is described for constructing a set of input patterns able to detect every given failure of a combinational network. The result may not be a minimal set of tests, but it is surely a complete test. The procedure is designed for large networks with high number of independent inputs. It can deal with networks including any elementary logical gates such as AND, OR, NAND, NOR, and NOT. No limitations on fan-out are considered. The method can treat any class of single or multiple logical failures which can be described by means of a transformation of the logic equations of the network. The conventional description of the failures as one wire stuck at one or stuck at zero is not required. This can be useful in detection of wiring errors in equipment testing. The basis of the procedure is a ``choice technique'' which avoids, in most cases, the two-level expansion of the mapping realized by the network. The procedure is illustrated in detail and two application examples to the detection of a single wire stuck at zero failure and of a wiring error are given. View full abstract»

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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope