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Electronic Computers, IEEE Transactions on

Issue 1 • Date Feb. 1967

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Displaying Results 1 - 25 of 42
  • [Front cover]

    Page(s): c1
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  • IEEE Computer Group

    Page(s): nil1
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  • [Breaker page]

    Page(s): nil1
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  • Editor's notice [Change of Associate Editor]

    Page(s): 1
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  • Iterative Analog Computation and the Representation of Signals

    Page(s): 2 - 8
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    The advent of iterative analog computers has greatly increased the class of problems that can efficiently be simulated with a hybrid system. The iterative analog computer has placed wide bandwidth analog components under the control of high-speed digital logic. This enables one both to increase the sophistication of the control used for the analog components and to acquire statistically significant samples of the process in a reasonable period of time. An iterative analog computer has been used to investigate methods of increasing the efficiency of signal representation systems by combining analog measurements with digital control and storage. A hybrid system has been developed that is capable of adjusting the exponential basis as well as the coefficients of the representation to minimize the integrated squared error between a signal and its representative. Since the efficiency of the representation depends upon the sampling instant chosen for measurement of the coefficients, methods of detecting this instant were investigated. A detection system has been developed that can adaptively adjust its parameters to correspond to the signal that is being processed. The data presented illustrates the dynamic accuracy of the iterative analog computer, the convergence properties of the optimization procedure, and the statistical properties of the detector when noise is present. View full abstract»

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  • Analog and Digital Computation of Fourier Series and Integrals

    Page(s): 8 - 13
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    In engineering and scientific problems one of the most commonly used tools is Fourier analysis. With the increasing availability of analog, hybrid, and digital computers, it is useful to examine special techniques applicable to these machines. This paper presents: 1) methods for evaluating the required integrals on either a digital or an analog computer and 2) an analysis which results in guidelines for choosing the sampling interval when the problem is done digitally. Parts of the material presented in this paper can be found in other sources although there are some refinements included here that make the implementation of the theory considerably easier. The theory is valid for any machine, but minor modifications may have to be made in hybrid computer patching or in the digital program to conform with equipment restrictions. View full abstract»

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  • Calculation of Cross-Coupled Noise in Digital Systems

    Page(s): 14 - 17
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    This paper deals with a mathematical method of finding cross-coupled noise-voltage in digital equipment. A formula is derived which permits, either strictly mathematical or with some approximations, calculation of noise, thus providing a means for a mathematical approach to interconnection design. View full abstract»

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  • The Minimization of TANT Networks

    Page(s): 18 - 38
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    A TANT network is a three-level network composed solely of AND-NOT gates (i.e., NAND gates) having only true (i.e. uncomplemented) inputs. The paper presents an algorithm for finding for any given Boolean function a least-cost (i.e. fewest number of gates) TANT network. The method used is similar to the Quine-McCluskey algorithm for two-level AND/OR networks. Certain functions realizable by input gates or second-level gates are preselected as candidates for possible use in an optimal network. This is analogous to the preselecting of prime implicants in two-level minimization. A network is then obtained by choosing a least-cost subset of the candidates which is adequate for realizing the function. This selection phase is analogous to the use of a prime implicant table in two-level minimization. In TANT minimization, however, an extension to a prime implicant table known as a CC-table must be used. The algorithm permits hand solution of typical four-and five-variable problems. A computer program has been written to handle more complex cases. View full abstract»

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  • Three-Valued Propositional Calculus of Lukasiewicz. and Three-Position Double Switches

    Page(s): 39 - 44
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    This paper establishes a clear relation between the trivalent propositional calculus of Lukasiewicz and circuits with double switches of three positions. Adequate alphabet, language and semantics are defined in order to accomplish the aforesaid relation. Two circuit configuration properties occur: an axial symmetry, consequence of the duality exhibited by the Lukasiewicz's algebras, and a superposition phenomenon, closely related to the language. Finally, series and parallel Boolean electrical connections appear as a part of Lukasiewicz's infimum and supreme. View full abstract»

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  • On Determination of Optimal Distributions of Carry Skips in Adders

    Page(s): 45 - 58
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    The methods for determining the carry skip distributions in the adders with the minimum carry propagation time and the minimum number of carry skip circuits for a given carry propagation time are presented on the assumption that every adder position is comprised either in one skip at most or in two skips at most. Two types of adders with carry skips and each of them without and with end-around-carry are considered. The first one is a classical type of adder composed of identical one-position adders, the second is a NOR-gate adder containing 6 NOR-gates for one adder position only, and 1 NOR-gate for one position of the carry line only. These numbers of gates in the adder result in its economical advantages and relatively small carry propagation time as compared with many other adders. The presented skip distributions demand a relatively small number of skips and give a significant reduction in the carry propagation time. View full abstract»

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  • Experiments on Models of Computations and Systems

    Page(s): 59 - 69
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    This paper reports results of experiments on models of computational sequences and models of computer systems. The validity of these models is a step in the evolution of methods for prediction of complex computer system performance. A graph model representing computational sequences was implemented and mapped onto a model of computer systems using programmable assignment and sequencing strategies. An approximate procedure for a priori estimation of path length (computation time) through an assigned graph was checked against more conventional simulation. The graph model was also perturbed to probe sensitivity of estimates of operation times, cycle factors, and branching probabilities. Problems arising in numerical weather prediction, X-ray analysis, nuclear modeling, and graph computations were transformed into acyclic directed graphs and have undergone computer analysis. Effectiveness of parallel processing, convergence properties of the successive approximation assignment and sequencing procedure, sensitivity to input parameter variation, the cost in computer time of the graph analysis, and comparison with more conventional SIMSCRIPT simulation are presented. The reduction in time required to obtain an estimate of path length compared to conventional simulation is found to range from a little less than 102 to more than 104. Computational tests indicate that additional factors may be gained without severe loss in validity of the approximation. View full abstract»

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  • Models of Computational Systems-Cyclic to Acyclic Graph Transformations

    Page(s): 70 - 79
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    This paper discusses cyclic to acyclic transformations performed on graphs representing computational sequences. Such transformations are critical to the development of models of computations and computer systems for performance prediction. The nature of cycles in computer programs for parallel processors is discussed. Transformations are then developed which replace cyclic graph structures by mean-value equivalent acyclic structures. The acyclic equivalents retain the noncyclic part of the structure in the original graph by evaluating a multiplicative factor associated with the mean time required for each vertex execution in the original graph. Bias introduced in the acyclic approximation is explored. View full abstract»

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  • Vector Integrators

    Page(s): 80 - 82
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    In this paper it is shown that it is impossible to realize a causal, linear, time-invariant two-port which integrates an arbitrary modulation on a suppressed carrier input while leaving the carrier unchanged. It is shown further that a realization of a four-port integrator is possible, provided the two inputs to the four-port have the same modulation but are on quadrature carriers. A specific realization of such an integrator, called a vector itegrator, is exhibited and its applications are discussed. View full abstract»

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  • Failure-Erasure Circuitry: A Duplicative Technique of Failure-Masking Systems

    Page(s): 82 - 85
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    This paper describes a logical redundancy technique based on failure-erasure circuitry that is capable of automatically masking as many as P¿1 individual failures in P identical elements connected in parallel. This technique is contrasted with the standard von Neumann scheme where only (P/2) such failures can be tolerated. In order to prevent the effect of any single failure from propagating, each logical element in the original network need only be duplicated rather than triplicated as in the von Neumann technique. The usefulness of the redundancy technique described is predicated on the existence of circuitry that fails to a NULL state rather than to a ZERO or ONE state. Accordingly, several circuits which exhibit the desired failure mode and that are worthy of further development for reliability applications are discussed. View full abstract»

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  • Ferromagnetic Wire Memory

    Page(s): 86 - 88
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    A nonvolatile NDRO memory utilizing a new concept is described. The concept is based on the recent discovery of a new electrodynamic phenomena which is related to the Procopiu effect. In its simplest form the memory consists of a ferromagnetic wire with a concentrically wound pickup coil. The memory operates on the principle that an EMF will be induced in a search coil wound over a ferromagnetic wire when the wire carries a pulse or alternating current and is under the influence of a stationary longitudinal magnetic field. The wire is not strained. Under such conditions the search coil produces an output or ``read'' signal whose polarity or phase, relative to the clock input to the ferromagnetic wire, is a function of the prior insertion of a unidirectional current into the wire. The clock or interrogate drive may be unipolar pulses or sinusoidal alternating current. In the first case the pickup coil produces negative or positive pulses, and in the latter case a sinusoidal output of the same frequency as the clock, in or 180° out of phase. View full abstract»

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  • On (d, k) Graphs

    Page(s): 90
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  • On the Strong Connectedness of the Direct Product

    Page(s): 90
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  • NOR-Gate Binary Adder with Carry Completion Detection

    Page(s): 90 - 92
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  • On the Complete Convergence of Bordered Nets

    Page(s): 92 - 93
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    A procedure is described for minimizing the number of states in an asynchronous sequential function when the restriction exists that the input cannot change while the sequential function is in an unstable state. Furthermore, a procedure is described for minimizing the number of states in a sequential function when the restriction also exists that each output can change at most once during the time required for a transition from one stable state to another. View full abstract»

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  • A Note on State Minimization of Asynchronous Sequential Functions

    Page(s): 94 - 97
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    A procedure is described for minimizing the number of states in an asynchronous sequential function when the restriction exists that the input cannot change while the sequential function is in an unstable state. Furthermore, a procedure is described for minimizing the number of states in a sequential function when the restriction also exists that each output can change at most once during the time required for a transition from one stable state to another. View full abstract»

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  • A Modification of Lee's Path Connection Algorithm

    Page(s): 97 - 98
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    It is shown that a set of diagnostic tests designed for a redundant circuit under the single-fault assumption is not necessarily a valid test set if a fault occurrence is preceded by the occurrence of some ( undetectable) redundant faults. This is an additional reason ( besides economy) for trying to eliminate certain kinds of redundancy from the circuit. However, single-fault analysis may remain valid for some types of redundancy which serve a useful purpose, such as the elimination of logic hazards in two-level circuits. View full abstract»

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  • Fault Detection in Redundant Circuits

    Page(s): 99 - 100
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    It is shown that a set of diagnostic tests designed for a redundant circuit under the single-fault assumption is not necessarily a valid test set if a fault occurrence is preceded by the occurrence of some (undetectable) redundant faults. This is an additional reason (besides economy) for trying to eliminate certain kinds of redundancy from the circuit. However, single-fault analysis may remain valid for some types of redundancy which serve a useful purpose, such as the elimination of logic hazards in two-level circuits. View full abstract»

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  • Ordering of Implicants

    Page(s): 100 - 105
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    First Page of the Article
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  • Contributors

    Page(s): 106 - 107
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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope