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IEEE Transactions on Electronic Computers

Issue 1 • Date Feb. 1967

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Displaying Results 1 - 25 of 42
  • [Front cover]

    Publication Year: 1967, Page(s): c1
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  • IEEE Computer Group

    Publication Year: 1967, Page(s): nil1
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  • [Breaker page]

    Publication Year: 1967, Page(s): nil1
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  • Editor's notice [Change of Associate Editor]

    Publication Year: 1967, Page(s): 1
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  • Iterative Analog Computation and the Representation of Signals

    Publication Year: 1967, Page(s):2 - 8
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2911 KB)

    The advent of iterative analog computers has greatly increased the class of problems that can efficiently be simulated with a hybrid system. The iterative analog computer has placed wide bandwidth analog components under the control of high-speed digital logic. This enables one both to increase the sophistication of the control used for the analog components and to acquire statistically significan... View full abstract»

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  • Analog and Digital Computation of Fourier Series and Integrals

    Publication Year: 1967, Page(s):8 - 13
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (988 KB)

    In engineering and scientific problems one of the most commonly used tools is Fourier analysis. With the increasing availability of analog, hybrid, and digital computers, it is useful to examine special techniques applicable to these machines. This paper presents: 1) methods for evaluating the required integrals on either a digital or an analog computer and 2) an analysis which results in guidelin... View full abstract»

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  • Calculation of Cross-Coupled Noise in Digital Systems

    Publication Year: 1967, Page(s):14 - 17
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (756 KB)

    This paper deals with a mathematical method of finding cross-coupled noise-voltage in digital equipment. A formula is derived which permits, either strictly mathematical or with some approximations, calculation of noise, thus providing a means for a mathematical approach to interconnection design. View full abstract»

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  • The Minimization of TANT Networks

    Publication Year: 1967, Page(s):18 - 38
    Cited by:  Papers (32)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3643 KB)

    A TANT network is a three-level network composed solely of AND-NOT gates (i.e., NAND gates) having only true (i.e. uncomplemented) inputs. The paper presents an algorithm for finding for any given Boolean function a least-cost (i.e. fewest number of gates) TANT network. The method used is similar to the Quine-McCluskey algorithm for two-level AND/OR networks. Certain functions realizable by input ... View full abstract»

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  • Three-Valued Propositional Calculus of Lukasiewicz. and Three-Position Double Switches

    Publication Year: 1967, Page(s):39 - 44
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (639 KB)

    This paper establishes a clear relation between the trivalent propositional calculus of Lukasiewicz and circuits with double switches of three positions. Adequate alphabet, language and semantics are defined in order to accomplish the aforesaid relation. Two circuit configuration properties occur: an axial symmetry, consequence of the duality exhibited by the Lukasiewicz's algebras, and a superpos... View full abstract»

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  • On Determination of Optimal Distributions of Carry Skips in Adders

    Publication Year: 1967, Page(s):45 - 58
    Cited by:  Papers (24)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2042 KB)

    The methods for determining the carry skip distributions in the adders with the minimum carry propagation time and the minimum number of carry skip circuits for a given carry propagation time are presented on the assumption that every adder position is comprised either in one skip at most or in two skips at most. Two types of adders with carry skips and each of them without and with end-around-car... View full abstract»

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  • Experiments on Models of Computations and Systems

    Publication Year: 1967, Page(s):59 - 69
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1579 KB)

    This paper reports results of experiments on models of computational sequences and models of computer systems. The validity of these models is a step in the evolution of methods for prediction of complex computer system performance. A graph model representing computational sequences was implemented and mapped onto a model of computer systems using programmable assignment and sequencing strategies.... View full abstract»

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  • Models of Computational Systems-Cyclic to Acyclic Graph Transformations

    Publication Year: 1967, Page(s):70 - 79
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1428 KB)

    This paper discusses cyclic to acyclic transformations performed on graphs representing computational sequences. Such transformations are critical to the development of models of computations and computer systems for performance prediction. The nature of cycles in computer programs for parallel processors is discussed. Transformations are then developed which replace cyclic graph structures by mea... View full abstract»

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  • Vector Integrators

    Publication Year: 1967, Page(s):80 - 82
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (570 KB)

    In this paper it is shown that it is impossible to realize a causal, linear, time-invariant two-port which integrates an arbitrary modulation on a suppressed carrier input while leaving the carrier unchanged. It is shown further that a realization of a four-port integrator is possible, provided the two inputs to the four-port have the same modulation but are on quadrature carriers. A specific real... View full abstract»

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  • Failure-Erasure Circuitry: A Duplicative Technique of Failure-Masking Systems

    Publication Year: 1967, Page(s):82 - 85
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (932 KB)

    This paper describes a logical redundancy technique based on failure-erasure circuitry that is capable of automatically masking as many as P¿1 individual failures in P identical elements connected in parallel. This technique is contrasted with the standard von Neumann scheme where only (P/2) such failures can be tolerated. In order to prevent the effect of any single failure from propagating, eac... View full abstract»

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  • Ferromagnetic Wire Memory

    Publication Year: 1967, Page(s):86 - 88
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1460 KB)

    A nonvolatile NDRO memory utilizing a new concept is described. The concept is based on the recent discovery of a new electrodynamic phenomena which is related to the Procopiu effect. In its simplest form the memory consists of a ferromagnetic wire with a concentrically wound pickup coil. The memory operates on the principle that an EMF will be induced in a search coil wound over a ferromagnetic w... View full abstract»

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  • On the Equivalence of Finite-State Sequential Machine Models

    Publication Year: 1967, Page(s):88 - 90
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (555 KB)

    First Page of the Article
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  • On (d, k) Graphs

    Publication Year: 1967, Page(s): 90
    Cited by:  Papers (15)
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  • On the Strong Connectedness of the Direct Product

    Publication Year: 1967, Page(s): 90
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  • NOR-Gate Binary Adder with Carry Completion Detection

    Publication Year: 1967, Page(s):90 - 92
    Cited by:  Papers (4)
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  • On the Complete Convergence of Bordered Nets

    Publication Year: 1967, Page(s):92 - 93
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (419 KB)

    A procedure is described for minimizing the number of states in an asynchronous sequential function when the restriction exists that the input cannot change while the sequential function is in an unstable state. Furthermore, a procedure is described for minimizing the number of states in a sequential function when the restriction also exists that each output can change at most once during the time... View full abstract»

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  • A Note on State Minimization of Asynchronous Sequential Functions

    Publication Year: 1967, Page(s):94 - 97
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (786 KB)

    A procedure is described for minimizing the number of states in an asynchronous sequential function when the restriction exists that the input cannot change while the sequential function is in an unstable state. Furthermore, a procedure is described for minimizing the number of states in a sequential function when the restriction also exists that each output can change at most once during the time... View full abstract»

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  • A Modification of Lee's Path Connection Algorithm

    Publication Year: 1967, Page(s):97 - 98
    Cited by:  Papers (51)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (375 KB)

    It is shown that a set of diagnostic tests designed for a redundant circuit under the single-fault assumption is not necessarily a valid test set if a fault occurrence is preceded by the occurrence of some ( undetectable) redundant faults. This is an additional reason ( besides economy) for trying to eliminate certain kinds of redundancy from the circuit. However, single-fault analysis may remain ... View full abstract»

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  • Fault Detection in Redundant Circuits

    Publication Year: 1967, Page(s):99 - 100
    Cited by:  Papers (60)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (424 KB)

    It is shown that a set of diagnostic tests designed for a redundant circuit under the single-fault assumption is not necessarily a valid test set if a fault occurrence is preceded by the occurrence of some (undetectable) redundant faults. This is an additional reason (besides economy) for trying to eliminate certain kinds of redundancy from the circuit. However, single-fault analysis may remain va... View full abstract»

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  • Ordering of Implicants

    Publication Year: 1967, Page(s):100 - 105
    Cited by:  Papers (9)
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    First Page of the Article
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  • Contributors

    Publication Year: 1967, Page(s):106 - 107
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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope