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Electronic Computers, IEEE Transactions on

Issue 4 • Date Aug. 1966

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Displaying Results 1 - 25 of 62
  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Group

    Page(s): nil1
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    Freely Available from IEEE
  • [Breaker page]

    Page(s): nil1
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    Freely Available from IEEE
  • IEEE Proceedings Computer Issue

    Page(s): 419
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    Freely Available from IEEE
  • The Special Issue on High-Speed Memories

    Page(s): 420 - 422
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    The design and performance characteristics of a 128×64 MOS transistor memory is given. The storage cell used operates with a low standby power, 0.1 mW. The memory operates with a 12-ns access time, 35-ns read cycle time, and a 60-ns write cycle time. View full abstract»

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  • An Investigation of the Potential of MOS Transistor Memories

    Page(s): 423 - 427
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    The design and performance characteristics of a 128X64 MOS transistor memory is given. The storage cell used operates with a low standby power, 0.1 mW. The memory operates with a 12-ns access time, 35-ns read cycle time, and a 60-ns write cycle time. View full abstract»

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  • An Experimental Nondestructive Microwave Ferrite Core Readout Using Stripline

    Page(s): 428 - 435
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    A static ferrite storage readout technique is described which utilizes microwave transmission phenomena rather than voltage induction to achieve readout. Reversible, rotational impulse switching is used to effect nondestructive interrogation of a small toroidal core which is coupled to a strip-type ``sense line.'' The core coupled to the stripline causes an electrically controllable discontinuity in the transmission line. The change of stripline transmission characteristics during interrogation, in turn, is dependent upon the remnant state of the core. Detection of a microwave signal transmitted through the stripline yields a bipolar signal which may be used to identify the remnant state of the core. The microwave readout technique which utilizes an XN-band signal permits readout of information in an extremely short duration of time. Experimental results are given to demonstrate readout in as little time as 3 nanoseconds. Utilization of the technique for readout of information from a mass memory configuration is potentially possible. View full abstract»

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  • Fast Nondestructive Read, Slow Write Memory Device Using Thick Magnetic Films

    Page(s): 435 - 441
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    A device is proposed for providing an ultra high speed read, but comparatively slow write, memory device. The device has certain similarities to other proposed devices, but the mode of operation and performance is quite new and makes use of effects which are normally avoided or minimized in usual memory devices. The storage element is a thick-film bias magnet with a coercive force smaller than its self-demagnetizing field and is tightly coupled to a second anisotropic thick film which serves as the sensing or reading device. The array conductors are all external to the coupled structure (i.e., no conductors lie between the films) thereby simplifying fabrication. A modified coincident current technique is used to write the information into the bias film. A stored ``1'' is obtained by setting the bias film and hence the read film into a demagnetized state. A read current applied to the word line will cause rotation of the magnetic moments of the read film toward its hard axis, thus inducing a signal in the sense line. A stored ``0'' is obtained by saturating the bias film, which in turn saturates the read film in its hard direction and thus prevents any signal from being induced in the sense line during reading. The modes of operation and design parameters are presented as well as a number of measurements. The results thus far have shown that there are no fundamental barriers to overcome. View full abstract»

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  • Woven Wire Memory for NDRO System

    Page(s): 442 - 451
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    A 4096 word NDRO memory system using the high speed woven wire memory is discussed. The operating principle and the NDRO characteristics of the memory together with stack construction, noise problems, circuitry, and experimental results are explained. The memory weave consists of electroplated magnetic thin-film wires for the digit-sense lines and insulated wires for the word lines, which are mounted on a terminal plate to form a plane. The stack is made up of 32 planes. To minimize noise effects, the word lines are diode-transformer matrix driven and the two-memory-cell per bit method is used in the digit-sense lines. The memory capacity is 4096 words × 10 bits. Cycle times of 400 ns for read and 600 ns for write, respectively, were achieved with high operating stability. View full abstract»

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  • Magnetic Film Scratch-Pad Memories

    Page(s): 452 - 458
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    An economic comparison has been made between fully integrated scratch-pad memories and thin magnetic-film scratch-pad memories on the basis of assumed component costs. On this basis, magnetic film memories are more expensive than fully integrated memories for very small memories, as expected. In terms of the assumptions made, the economic crossover as a function of memory size between the two memory types lies between 500 and 10 000 bits of storage. Two sample thin-film scratch-pad memory designs are given which have comparatively simple electronic circuitry using integrated circuit power supplies. This electronic circuitry also is amenable to integrated or hybrid circuit implementation. View full abstract»

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  • A Thin-Film Rod Memory for the NCR 315 RMC Computer

    Page(s): 459 - 467
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    This paper describes a thin-film Rod memory that is used as the main store in the NCR Rod Memory Computer. The production procedure for the Rod storage element and the fabrication and assembly of the memory stack is outlined. The mode of operation of the memory is discussed. Line characteristics, design criteria, as well as a description of word, sense, digit and timing circuits are also presented. View full abstract»

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  • Propagation of Sense Signals in Large-Scale Magnetic Thin Film Memories

    Page(s): 468 - 474
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    A dynamic analysis has been made of the behavior of sense signals in large-scale magnetic thin film memories. The timed effects of attenuation, distortion, cross coupling and interconnection are superimposed on the transmitted waveforms. The computed signals can be used as a design guide to determine the length of sense lines, the number of intersecting word lines, the sense amplifier requirements, etc. The key limiting factors are the resistance of lines and the capacitance at the line intersections. Design criteria are discussed. View full abstract»

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  • 2 1/2 D High Speed Memory SystemsߝPast, Present, and Future

    Page(s): 475 - 485
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    A ferrite core memory system organization is discussed which offers a significant improvement in performance as well as a lower cost potential in larger memory sizes. Significant differences relative to other memory organizations are presented. The diode decoded drive system is discussed in some detail, presenting a frequency domain approach to memory system resonances. A particular system is described and the directions for future system development are presented. View full abstract»

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  • First-and Second-Order Ferrite Memory Core Characteristics and Their Relationship to System Performance

    Page(s): 485 - 501
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    The characteristics of ferrite memory cores are discussed and it is shown how these characteristics relate to the performance of memories with different organizations. First to be discussed are the different memory organizations (3D, 2¿D, and 2D) in which ferrite cores are used. The sense-digit plane configurations for typical systems are discussed and illustrated. Also discussed and illustrated are the primary and secondary response characteristics and it is shown how these characteristics affect the sense output voltage. Test procedures for determining these characteristics, without the necessity for building a complete memory plane, are given. The general considerations are discussed for selecting a core for an application using these test results; this is illustrated with a tabulation of results derived from the testing of a series of 30-mil memory cores. The paper concludes with a brief discussion of core stress sensitivity and temperature characteristics. View full abstract»

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  • The ``Braid'' Transformer Memory

    Page(s): 502 - 508
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    This report describes a read-only digital computer memory which utilizes a loom to ``braid'' information into a wire harness. The memory is called a braid memory and is a variation on the type of transformer memory first described by T. L. Dimond. Such memories are useful when permanence of information is desirable. Braids for the memory described in this report were made at the rate of 213 bits/hour including connections. The use of a loom makes braid manufacture both a fast and an economical process. A number of trade-offs between speed, capacity, and component count exist; hence, braid memories with many different characteristics can be made. The memory described in this report has a capacity of 16 384 words of 16 bits each. View full abstract»

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  • Content-Addressable and Associative Memory Systems a Survey

    Page(s): 509 - 521
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    This review of content-addressable memory and associative computer systems represents an attempt to consolidate and report nontechnically the direction in which numerous independent research programs have progressed during the last ten years. The paper reflects the views of a myriad of researchers on subjects of organization (configuration concepts), hardware elements, logical operations, speed, cost, size, software implications, applications, advantages and disadvantages. In a report of this type it is important to quote directly and indirectly from the researchers themselves, so that the trends or directions of their concepts may converge into meaningful information. Acknowledgement is made to those quoted (see bibliography references) since they represent the meat of this survey. The bibliography, although voluminous, is not necessarily complete. A number of reference sources may have been overlooked inadvertently. It is hoped, however, that the information and the bibliography will serve as a base for those entering into research connected with this rapidly developing concept. View full abstract»

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  • A Cutpoint Cellular Associative Memory

    Page(s): 522 - 528
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    Due to the rapidly growing technological ability to batch fabricate a large number of components on one substrate, it is economical and reliable to implement an associative memory by cellular arrays. Such an associative memory is presented in this paper. The proposed memory is word-organized, and its basic building blocks are cutpoint cells with various indices. All the bit-memories, word-sequential-control networks, word-match tag-networks, and bit-output networks have identical structures, and the proposed memory system is especially compatible with the manufacture of integrated circuit. The memory can perform the comparison, tag, writing and nondestructive reading processes in the parallel-by-bit form, as well as Lewin's sorting scheme for ordered retrieval. The dematching process is completely automatic. The memory sequential-control ontrol system does not use any ladder structure which is commonly employed in previous associative memory systems; hence the operation speed is largely increased. The stage delays for various operations are given, and may be employed to estimate the speed of the associative memory. View full abstract»

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  • Design Techniques of a Delay-Line Content-Addressed Memory

    Page(s): 529 - 534
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    This paper describes a word-organized concept for retrieving information by means of word association which can be queried in, at most, one ``access'' time. An example of a 1000-word content-addressed memory (CAM) organization is given. It is shown that for a relatively simple logic organization worst-case word association times of 10 ¿s¿and even faster¿are possible. The memory organization for simple equality, pseudo-parallel equality, and between-limits searches is illustrated and discussed. These memory systems require the use of wide-band ultrasonic delay lines (using the most recent advances in ultrasonics, and not commercially available) and high speed (100-200 Mc/s) digital logic. The design, fabrication, and application of the parameters of these delay lines are discussed, based on experimental results achieved at Lockheed Electronics. The delay-line memory system can be both location-and-content-addressable, and has several advantages over the more common content-addressed (i. e., magnetic and cryogenic) memory systems. The systems described require little power and are physically small and lightweight. View full abstract»

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  • Present and Future State-of-the-Art in Computer Memories

    Page(s): 534 - 550
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    This paper presents a survey of the present state-of-the-art and anticipated future developments in read/write internal memories and on-line auxiliary memories. Functional uses of storage are discussed and advanced memory technologies are categorized by their applicability to each functional level in the storage hierarchy. Eight types of advanced solid-state memories are discussed briefly. Characteristics anticipated for these memories by 1970 in high speed control and scratch-pad memory, main internal memory, and solid-state on-line auxiliary storage applications are compared. Characteristics anticipated by 1970 for seven types of electromechanical auxiliary storage are also compared. The system implications of advanced memory technologies are considered from the standpoints of machine organization, programming, system organization, and computer users. Problems in the selection, utilization, and application of advanced memory capabilities are identified. The major contenders in each functional category for future memory systems are listed. View full abstract»

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  • Internal State Assignments for Asynchronous Sequential Machines

    Page(s): 551 - 560
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    The paper presents three procedures for coding the internal states of asynchronous sequential switching circuits. Resulting codes insure that the circuit will function according to flow table specifications independent of variations in transmission delays within the circuit. The assignment methods produce codes that allow one to maximize the operating speed of the circuit and are applicable to completely or incompletely specified sequential machines. View full abstract»

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  • Continuity and Realizability of Sequence Transformations

    Page(s): 560 - 569
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    In this paper we study some relations between the continuity of sequence transformations and their realizability by logic nets. The main results discussed include: the Curtis-Hedlund-Lyndon theorem which states that, if a sequence transformation is continuous and unitary (commutative with the shift transformation), then it can be realized by a net without feedback, and, the extension of this theorem to the finitary case. We find that unitary transformations are realized by definite automata, and finitary transformations are realized by indefinite automata. The term ``automata'' is used here in a modification of its usual sense, and we explore the relation between the conventional and modified notions. Many of the concepts and more significant mathematical results in this report can be found in another context in works by Hedlund and others. What may be new and of interest to computer scientists, we believe, is their application to the theory of sequential circuits. View full abstract»

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  • Analysis of Iterative NOR Autonomous Sequential Machines

    Page(s): 569 - 577
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    The autonomous behavior of an array of identical elements is investigated and found to be related closely to the structure of the array. Each element consists of a symmetric Boolean function of the inputs and one unit of delay. The interconnection of the elements is described by a matrix. A function in the element is universal and minimal if there exists an n×n interconnection matrix that will generate each of the autonomous state diagrams of 2n states. It is shown that no such function can exist. Assuming the NOR function in the element, theorems are presented that test the interconnection matrix in order to determine the autonomous behavior, i. e., state diagram, of the array. In particular, necessary and sufficient conditions for an array to generate a state diagram consisting entirely of cycles or rooted trees are described. If the array generates a cyclic state diagram, the cycle set can be determined from theorems derived in the paper. If the behavior is a rooted tree, theorems are presented that determine the state vector of the root, the maximum path length through the tree, and the number of states at a given distance from the root of the tree. View full abstract»

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  • A Tabular Minimization Procedure for Ternary Switching Functions

    Page(s): 578 - 585
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    A tabular minimization procedure for ternary switching functions is developed. The theory is analogous to that used in the McCluskey simplification method for Boolean functions. Using the ternary function truth table, the procedure provides a systematic method of applying a limited set of reduction rules in a converging process for obtaining a minimal irredundant form of the function. It is shown how the procedure can be used to derive simplified expressions for arbitrary ternary functions in terms of a particularly attractive system of threshold gating functions. The procedure has more general applications in providing a simple method of finding, for any given function, all binary variables of the function and all variables of which the function is independent. View full abstract»

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  • On Nonlinear Binary Sequential Circuits and Their Inverses

    Page(s): 586 - 596
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    This paper discusses single-input, single-output binary sequential circuits composed of adders, multipliers and delay units. The principal results are: 1) Finite feedforward circuits are characterized by a response function (rf) which permits the determination of the output for an arbitrary input. 2) Corresponding to every rf is a transfer function (tf) which is obtained by a multidimensional Z-transform of the rf. This tf permits the determination of the response of a feedforward circuit by transform domain techniques. 3) Every tf may be synthesized as a physical circuit. 4) A canonic form is defined for every tf. With this canonic form is identified an implementation which contains a minimum number of delay units and adders. 5) Nonfeedforward circuits are called well defined if they meet certain physically meaningful restrictions. 6) Well-defined circuits may be classified as those which have inverses (class I) and those which do not. Membership in class I is shown to be a property of circuits which established one-one maps of inputs onto outputs. Circuits which do not belong to class I have neither left nor right inverses. 7) An intimate connection between inverses and feedback circuits is established. It is shown that any well-defined feedback circuit and a related circuit in I are mutually inverse. 8) It is shown that the necessary and sufficient condition for a feedback circuit to be well defined is that the circuit in the feedback loop contains delay. View full abstract»

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  • Generalized Snake-in-the-Box Codes

    Page(s): 596 - 602
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    A snake-in-the-box (SIB) code of order k is defined to be an ordered sequence of binary code words in which adjacent words differ in only one bit, and pairs of code words that are k or more apart in the ordered sequence differ in at least k bit positions. In this paper, constructions for SIB codes of arbitrary order are given, as well as upper bounds on the maximum code sequence length for given order and word size. These codes are potentially useful for binary encoding of analog data. Gray codes are SIB codes of order one, and Kautz has investigated SIB codes of order two. The SIB codes of a given order contain as a subset all SIB codes of higher order. View full abstract»

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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope