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Electronic Computers, IEEE Transactions on

Issue 4 • Date Aug. 1965

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Displaying Results 1 - 25 of 47
  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Group

    Page(s): nil1
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    Freely Available from IEEE
  • [Breaker page]

    Page(s): nil1
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    Freely Available from IEEE
  • New Editor-in-Chief

    Page(s): 533
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    Freely Available from IEEE
  • A Reduction Technique for Prime Implicant Tables

    Page(s): 535 - 541
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    Solving prime implicant tables is greatly facilitated by reduction techniques such as row dominance, column dominance, and essential row selection. This paper presents a new reduction technique which is operable on any otherwise irreducible table having a column covered by exactly two rows. View full abstract»

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  • Average Values of Quantities Appearing in Multiple Output Boolean Minimization

    Page(s): 542 - 552
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    In connection with the problem of two-level minimization of systems of Boolean functions, formulas are obtained for the following statistical quantities: average number of k cubes, prime k cubes, and essential k cubes of a system of Boolean functions. The parameters appearing in the formulas are the number of variables, the number of functions of the system, and the number of ``one'' vertices of each function. Numerical evaluations are given. Increasing by one the number of variables n of a system of m functions roughly results in multiplying the average numbers of cubes and prime cubes by a factor of about 2.2 to 2.3. The ratio of the average numbers of essential cubes and prime cubes rapidly decreases increasing n or m, so that the minimization algorithms, which obtain the essential cubes before the prime cubes, seem statistically unsuitable to solve ``large'' minimization problems. The average occupation memory occurring in Quine, McCluskey, and Bartee algorithms is also evaluated. Its rate of increase with the number of variables is about 2.5. View full abstract»

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  • Synthesis of Minimal Threshold Logic Networks

    Page(s): 552 - 560
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    An algorithm is developed for synthesizing networks which realize Boolean switching functions through the use of a minimum number of threshold logic elements. A switching function is represented by a matrix and the algorithm is based on the principle that the removal of the positive linear dependences from the rows of this matrix results in a linearly separable function. The positive linear dependences are removed by adding columns to the matrix, each column representing the output of a threshold logic element in the network. The added columns in effect transform a nonseparable function into a sparable function a higher dimensional space. The algorithm is illustrated with examples of the synthesis of both single and multiple output networks. The technique is not restricted to completely specified functions. View full abstract»

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  • On Information Lossless Automata of Finite Order

    Page(s): 561 - 569
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    A coding graph is a model which contains all the types of finite automata and codes as special cases. A test for information losslessness and for information losslessness of finite order of a coding graph is described. Efficient methods of computation are given which make the calculation simple and mechanizable. The application of the tests to finite deterministic automata is discussed and a method of constructing a decoder for a given finite automaton that is information lossless of finite order, is described. View full abstract»

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  • Design of an Accumulator for a General Purpose Computer

    Page(s): 570 - 574
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    This paper describes the logical design of an accumulator register for a general purpose digital computer. The only logic gates used are NOR gates and inverter gates and the sole storage device is a gated clocked flip-flop which takes the value on a single input line when the gate line is high. The accumulator register operates in conjunction with another register called the memory exchange register. The memory exchange register can be added to the accumulator, subtracted from the accumulator, ANDed with, and ORed with the accumulator; the result in each case being placed in the accumulator. The accumulator can also be shifted right or left. The problem of carry propagation during addition is alleviated by carry bridging. The accumulator circuitry has been made simpler by treating the operations to be performed collectively rather than individually, and by careful assignment of input-values to the storage devices. View full abstract»

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  • Transmission Capacity of Disk Storage Systems with Concurrent Arm Positioning

    Page(s): 575 - 582
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    An organization for a disk storage system oriented toward multicomputer and shared computer applications is described, and a study is made of its effectiveness in accessing data. The disk file incorporates an independently positioned arm for accessing each disk, and the capability for concurrently controlling several positioners. Also, multiple data transmission channels can be provided between the disk file and a buffer unit. A criterion of maximum average transmission capacity is proposed for investigating the speed of accessing data with this organization. Probabilistic models for analyzing the queueing of positioned arms for access to a disk-buffer transmission channel are developed. With reasonable assumptions, the solution of the models is reduced to a small set of linear equations in terms of queue length probabilities. The transmission capacity is evaluated with parameter values typical of contemporary disk files. The principal conclusion is that the economic feasibility of more than three position controllers per disk-buffer channel is very doubtful in seeking the full effectiveness of this organization. View full abstract»

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  • The Scaling of Digital Differential Analyzers

    Page(s): 583 - 590
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    A method for computing the scales needed for programming a digital differential analyzer (DDA) is developed. DDA program (interconnection) maps containing integrators and servos are considered. The scales must satisfy ``equilibrium,'' ``topological,'' and ``boundary'' constraints. These constraints are shown to be equivalent to a set of linear inequalities. Linear programming techniques are used to find both feasible and ``optimal'' scales. The use of linear programming eliminates the need for the usual trial-and-error scaling techniques and makes the scheme amenable to programming on a general-purpose digital computer. View full abstract»

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  • Worst-Case Considerations in Designing Logical Circuits

    Page(s): 590 - 599
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    A method of design is presented for logical circuits, starting from worst-case considerations. The method represents an approach to dc optimization. Special attention is paid to temperature and tolerance problems in monolithic integrated circuits. In the worst-case design procedure outlined, the requirements for obtaining a properly functioning circuit are taken as the point of departure. This results in a whole field of possible circuits from which¿depending on further specifications¿it is comparatively easy to find special solutions. Three examples of worst-case calculations are developed¿one for a transistor-transistor logic circuit, one for a diode-transistor logic circuit, and finally, one for a new type of circuit, termed emitter-follower transistor logic. View full abstract»

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  • A Destructive-Readout Associative Memory

    Page(s): 600 - 605
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    The organization of an associative memory which makes use of conventional destructive-readout magnetic elements is presented. The associative memory described is word-organized; an example is an array of memory elements of 64 bits by 1024 bits. The memory is both location-addressable and content-addressable, and capable of bit-parallel search. A unique feature is its two-dimensional read/write capability, resulting (for the example) in a short-word length of 64 bits and a long-word length of 1024 bits. Such an associative memory is proposed mainly for nonnumerical data processing rather than for storage. The bit-parallel search logic is not embedded in each memory element, but is implemented for a long-word at the exterior of the memory array. As a result, this associative memory is less costly than an associative memory where parallel logic is built into each memory element. Because parallel-search logic is implemented for only one long-word, implementation of several varieties of search logic is practical. In addition to a bit-comparison logic, other logical operations (such as NAND, NOR, AND, OR) can be implemented relatively simply and less expensively. View full abstract»

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  • Delay Approximations for Correlation Measurements Using Analog Computers

    Page(s): 606 - 617
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    In the most direct method for measuring correlation functions with an analog computer a delay must be simulated. Since a lumped parameter system is used, we can only hope to approximate this delay. We intentionally exclude such storage systems as magnetic tapes because of their cost, and confine ourselves to the use of commonly available analog computer components. Extensive work has been carried out toward finding the best delay approximation according to different criteria, based mainly on transient or frequency response considerations. In this paper a new point of view is adopted. The overall effect of the delay approximation on the measured value of the autocorrelation function is taken into account. The best approximation is then chosen as the one that produces the closest agreement between the theoretically measured value and the exact value of the autocorrelation. It is seen that this method for selecting the delay approximation sometimes leads to very different results from those formerly obtained. For example, it is shown that for measuring the autocorrelation of noise generated by filtering white noise with a filter with real poles, the best approximation is one whose value for a real argument (instead of j¿) best approaches the exponential function for a real argument. The treatment of the subject in this paper deals mainly with the autocorrelation function, but is later extended to the case of cross-correlations. View full abstract»

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  • Experimental Study of a New Method of Time Delay for Analog Computers

    Page(s): 617 - 623
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    A new method for obtaining pure delay of voltage waveforms on the analog computer is discussed. This method, which is based upon frequency-domain sampling in combination with a feedforward-feedback technique, is capable of producing relatively long delays. The theory underlying the method has been previously presented. In this paper experimental aspects are described in detail. Particular emphasis is placed upon those topics that are important to the use of the method in actual practice, namely; 1) a general, scaled computer diagram, 2) typical experimental records (which also verify the theory), and 3) a general procedure for programming and debugging. The experimental study has shown that high-quality results are obtainable with this method. Moreover, it is widely applicable to computation and simulation problems, and can easily be programmed. View full abstract»

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  • An Algorithm for Threshold Element Analysis

    Page(s): 623 - 625
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    A majority or threshold element is a device with a finite number of inputs and a single output. The output, Fn is a Boolean function of the n binary valued variables (x1, x2, ..., xn) applied to the inputs. The analysis of a threshold element is the determination of the output Boolean function, Fn when the input variables and their multiplicities are specified. The multiplicity of an input variable xi is the number of inputs to which the variable is applied. The fundamental problem in analysis is the determination of Fn when the number of inputs is moderately large. An algorithm is given which permits a simple straightforward determination of Fn in reduced, disjunctive form. View full abstract»

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  • On the Dual-Monotonicity of Threshold Functions

    Page(s): 625 - 627
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    A necessary condition for a threshold function in terms of comparability was first reported by Paull and McCluskey [4] who have established a chain of conditions later called 1-monotonicity, 2-monotonicity, and k-monotonicity, in general. Each of these conditions entails its predecessors, and is stricter than them; the union of this denumerable set of conditions is called complete monotonicity by Winder. Winder [5] has given an extensive treatment of these ideas and has offered an efficient procedure for the design of threshold devices. View full abstract»

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  • Matrix Criteria for Arbitrary Reliability in Iterated Neural Nets

    Page(s): 627 - 629
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    In a previous paper by this author, the problem of achieving arbitrary reliability for combinatorial nets from arbitrarily unreliable elements was reduced to the study of the convergence properties of an associated polynomial system. In this paper simple criteria which specify the convergence of such a system to a nodal fixed point are obtained from known results in matrix theory. (Convergence to a nodal fixed point implies that the corresponding net approaches reliability arbitrarily near 1 for a particular function.) Theorems are also given which show that it is possible to obtain, from a single system converging to a nodal fixed point, many systems having this property. In a recent paper by this author [1] the organization and reliability of large combinatorial nets were investigated. In that paper several theorems were proved whose ultimate purpose was to delineate conditions under which arbitrarily reliable homogeneous nets could be obtained from arbitrarily unreliable elements. It is the main purpose of the present note to amplify these results as well as prove certain new theorems from which arbitrary reliability for a particular net may be tested by making use of easily applied theorems and associated algorithms. We begin by reviewing certain necessary concepts from the aforementioned paper. This paper should be consulted for a more detailed treatment of these ideas. View full abstract»

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  • Some Problems in Relay Circuit Design

    Page(s): 630 - 634
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    In the design of sequential relay circuits one often has to consider the circuit as a part of a larger system, and one must take into account the nature of the inputs to the circuit. Frequently, the inputs are two-terminal contact networks with one terminal grounded; such inputs will be called simple. This paper examines the formal design techniques as applied to circuits with simple inputs. It is shown that all relays should be considered as secondary, from the point of view of both races and minimization. Several other shortcomings of the present theory are pointed out. Properties of circuits with simple inputs are examined. It is shown that there are flow tables not realizable without races with simple inputs, and that the presently known secondary assignment methods are not applicable to circuits with simple inputs. View full abstract»

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  • Comments on the Minimization of Stochastic Machines

    Page(s): 634 - 637
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    In a recent note by Bacon [1], a new result about the minimization of stochastic finite state machines has been proven. Extending the theory developed by Carlyle [2], he shows that all minimal-state forms of equivalent machines are state equivalent, and they all have the same number of states. He also describes a necessary and sufficient condition for a machine to be minimal. View full abstract»

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  • "Light-Pen"' Facilities for Direct View Storage Tubes-An Economical Solution for Multiple Man-Machine Communication

    Page(s): 637 - 639
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    Techniques are presented which enable conventional "light-pen" tracking and pointing functions to be extended to the direct view storage tube (DVST). The schemes eliminate the high data transfer rates or considerable buffer storage required even for static displays when short persistence cathode ray tubes (CRTs) are used. Two solutions, a "quadruple photo-sensor pen" and the "potentiometer pen" (a transparent resistive sheet and stylus combination which covers the display), are described and compared. View full abstract»

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  • A Shiftrix for High-Speed Multiplication

    Page(s): 639 - 643
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    The concept of the shiftrix matrix is due to Dr. G. Estrin [1] of the UCLA Department of Engineering. In broad terms the shiftrix is a device for speeding up the multiplication operation in computers by making use of complete parallelism in the shifting operation to reduce the total shifting time to a negligible value. A similar device to accomplish the same purpose has been devised by Richards [2]. View full abstract»

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  • Figure of Merit of Electronic Switching Devices

    Page(s): 643 - 646
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    To specify the amplifying properties of various active electronic devices the gain-bandwidth product GNB is commonly used. The aim of this paper is to show that for active electronic (not electromagnetic) devices working in switching circuits, another figure of merit (analogous to the reciprocal of the gain-bandwidth product) could be derived from a simple model of an electronic switch. View full abstract»

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  • A Functional Counter

    Page(s): 646 - 647
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    First Page of the Article
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  • Comment on NOR-NAND Synthesis

    Page(s): 648
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    First Page of the Article
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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope