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IEEE Transactions on Electronic Computers

Issue 3 • Date June 1965

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Displaying Results 1 - 25 of 54
  • [Front cover]

    Publication Year: 1965, Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Group

    Publication Year: 1965, Page(s): nil1
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    Freely Available from IEEE
  • Breaker Page

    Publication Year: 1965, Page(s): nil1
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    Freely Available from IEEE
  • Enumeration of Seven-Argument Threshold Functions

    Publication Year: 1965, Page(s):315 - 325
    Cited by:  Papers (126)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2107 KB)

    A tabulation of the 2470 representative threshold functions of seven arguments has been prepared by the author. This paper discusses the methods used in, and the threshold logic implications of, the enumeration. The self-dual classification method of Goto-Takahasi was employed. A lattice was defined on the 8-cube in terms of which all 2-monotonic, canonical, self-dual functions of eight arguments ... View full abstract»

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  • Geometrical and Statistical Properties of Systems of Linear Inequalities with Applications in Pattern Recognition

    Publication Year: 1965, Page(s):326 - 334
    Cited by:  Papers (585)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1589 KB)

    This paper develops the separating capacities of families of nonlinear decision surfaces by a direct application of a theorem in classical combinatorial geometry. It is shown that a family of surfaces having d degrees of freedom has a natural separating capacity of 2d pattern vectors, thus extending and unifying results of Winder and others on the pattern-separating capacity of hyperplanes. Applyi... View full abstract»

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  • Computing Irredundant Normal Forms from Abbreviated Presence Functions

    Publication Year: 1965, Page(s):335 - 342
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1469 KB)

    A new method is presented for computing irredundant normal forms which renders feasible the handling of ``large'' functions. The method is based on the concept of abbreviated presence function and incorporates techniques found in the methods of ratio function and iterated consensus of the prime implicants. The complete set of irredundant normal equivalents of a formula is shown to be obtainable fr... View full abstract»

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  • State Assignments in Combinational Networks

    Publication Year: 1965, Page(s):343 - 349
    Cited by:  Papers (9)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1278 KB)

    The problem of assigning codes to the output states of a multiple-output combinational circuit is considered. It is assumed that if the circuit has n inputs, then the 2n fundamental products, i.e., input states, are to be partitioned into disjoint groups, such that all members of the same group produce the same output state. The problem of coding the output states is studied here. Two a... View full abstract»

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  • A Method for Minimizing the Number of Internal States in Incompletely Specified Sequential Networks

    Publication Year: 1965, Page(s):350 - 359
    Cited by:  Papers (87)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1764 KB)

    A method is illustrated for minimizing the number of internal states in incompletely specified sequential networks. The minimization algorithm applies to any type of incompletely specified flow table. It is shown that only some compatibility classes (prime compatibility classes) need be considered as members of a solution. The selection of prime classes may be obtained as the solution of an intege... View full abstract»

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  • Synthesis of Error-Tolerant Counters Using Minimum Distance Three State Assignments

    Publication Year: 1965, Page(s):359 - 366
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1634 KB)

    It is shown that by using minimum distance three state assignments and considering error states when deriving the input equations, counters tolerant of a single error can be synthesized. Although one flip-flop in the counter might be in error, the other flip-flops will continue to sequence correctly. Thus acceptable sequencing continues with a malfunctioning unit present in the circuit. Because of... View full abstract»

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  • Identification and Minimization of Linear Machines

    Publication Year: 1965, Page(s):367 - 376
    Cited by:  Papers (21)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1454 KB)

    This paper is a study of linear machines and their submachines. Methods are presented for finding the reduced form of a given linear machine with or without fixed initial state. A technique is suggested for detecting whether a machine is linear or can be embedded as a submachine in a linear machine. In the latter case a state assignment is produced for the minimum linear realization. Encoded input... View full abstract»

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  • Sequential Functions and Linear Sequential Machines

    Publication Year: 1965, Page(s):376 - 382
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1276 KB)

    The``state'' of a sequential machine is interpreted as the sequence-to-sequence input-output mapping performed by the machine. Such mappings have been called sequential functions. This concept of state is applied to the theory of binary linear sequential machines. The modulo-2 adders are assumed to have an inherent delay td¿0, and the effects of initial conditions are considered. The p... View full abstract»

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  • Antiparallel Control Logic

    Publication Year: 1965, Page(s):383 - 393
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2387 KB)

    This paper proposes a method, termed antiparallel control logic, for the control and efficient utilization of computer networks that exhibit substantial propagation delays on the lines interconnecting the logical elements, as well as in the elements themselves. The discussion encompasses the basic behavior of antiparallel stages that realize this method of control, including their logical realizat... View full abstract»

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  • A One-Dimensional Real-Time Iterative Multiplier

    Publication Year: 1965, Page(s):394 - 399
    Cited by:  Papers (35)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1094 KB)

    The class of one-dimensional, real-time, iterative, discrete-state automata is described. By example, it is shown that serial multiplication can be carried out by such a sequential switching network. Each of two arbitrarily large integers is represented in binary notation by a time sequence of digits 0 or 1, the lowest order digits first. A design is given for a discrete-state machine that has as ... View full abstract»

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  • ILLIAC II-A Short Description and Annotated Bibliography

    Publication Year: 1965, Page(s):399 - 403
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1118 KB)

    ILLIAC II is a general purpose computer built at the University of Illinois, Urbana. It contains about 55000 transistors and has a floating multiply time of 6.3 μs. A number of features are provided to increase the speed of operation. There are three controls in largely concurrent operation. The control circuits are largely asynchronous and speed independent. The floating point arithmetic ... View full abstract»

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  • LOCS: An EDP Machine Logic and Control Simulator

    Publication Year: 1965, Page(s):403 - 416
    Cited by:  Papers (3)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2390 KB)

    The new EDP Machine Logic and Control Simulator, LOCS, is designed to facilitate the simulation of data processing systems and logic on the IBM 7090 Data Processing System. With this simulator, it will be possible to operate and execute commands in a manner comparable to that of a hardware version of the machine being simulated. The inputs to LOCS consist of a description, coded in LOCS language, ... View full abstract»

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  • Direct Execution of Programs in Floating Code by Address Interpretation

    Publication Year: 1965, Page(s):417 - 422
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1061 KB)

    This paper describes the use of a very high-speed scratch pad memory for directly executing programs in floating code with a single origin or multiple origins. When a program is being loaded into the magnetic core memory of a digital computer, there is no need of modifying the addresses of the original code. Neither the programmer, nor the operator, nor the program loader has to know where are the... View full abstract»

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  • A Versatile Comparator for Encoding Devices

    Publication Year: 1965, Page(s):423 - 427
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (774 KB)

    The complexity, speed, and accuracy of encoding systems depend strongly upon the type of voltage amplitude comparator used. Encoding techniques such as successive approximation and time base use only a single comparator while parallel encoding and nonprogrammed feedback encoding require at least one comparator for each stage. This paper presents a versatile voltage amplitude comparator with sugges... View full abstract»

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  • Fixed Resistor-Card Memory

    Publication Year: 1965, Page(s):428 - 434
    Cited by:  Papers (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (3162 KB)

    A fixed or read-only memory, consisting of a stack of paper or plastic punched cards, each containing an interconnected array of printed resistors, is discussed. The cards are compatible with conventional keypunches, and information is recorded on each card by the punching of a pattern of holes, each of which severs an appropriate connection. An interconnection method, which involves the injection... View full abstract»

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  • A Parapropagation Pattern Classifier

    Publication Year: 1965, Page(s):434 - 443
    Cited by:  Papers (7)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (2345 KB)

    A matrix of simple, identical intercommunicating cells is the core of a pattern classifier that can sort two-valued, two-dimensional patterns, such as alphabetic symbols. The matrix yields information about a patterm mapped on its cells by reporting whether or not a threshold exceeds the number of cells that remain in a ``zero'' state after a sequence of operations that include directed cell-to-ce... View full abstract»

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  • Acoustic Ray Tracing on the General-Purpose Electronic-Analog Computer

    Publication Year: 1965, Page(s):443 - 455
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1487 KB)

    A simulation of the trajectory of underwater acoustic rays is implemented on a general-purpose electronic-analog computer. Equations defining the phenomena are summarized, assumptions are listed, and a preferred form of the equations is developed to provide maximum attainable accuracy of solution. Included are considerations of the velocity of sound as an arbitrary function of both depth and range... View full abstract»

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  • Optimum Design of a Diode Squarer by Applying the Criterion of Square Root of the Integral of Per Cent Error Squared

    Publication Year: 1965, Page(s):456 - 463
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1415 KB)

    Quarter-square diode analog multipliers are composed of two diode squaring channels. The selection of the diode breakpoints and the output level at each of them involves essentially the optimization of a straight-line segment approximation to the ideal parabolic output. This optimization has often been discussed and actually carried out in commercial multipliers using the least value of the integr... View full abstract»

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  • On the Bound to the Memory of a Sequential Machine

    Publication Year: 1965, Page(s):464 - 466
    Cited by:  Papers (12)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (502 KB)

    Following Moore [1], consider a sequential machine (discrete, synchronius automata) having n states or less, m inputs, and p-possible outputs. The state that the machine is in at a given time depends only on the state at the previous time and the previous input. The output at a given time depends only on the current state. In addition the machine is strongly connected. That is to say, it is possib... View full abstract»

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  • An Improvement on a Theorem of E. F. Moore

    Publication Year: 1965, Page(s):466 - 467
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (439 KB)

    A necessary and sufficient condition for the existence of an autonomous clock in a sequential machine M is found to be the existence of a nontrivial input-independent partition on the set of internal states of M, no matter whether M is completely specified or incompletely specified. Two different techniques are given for generating the smallest input-independent partition ¿, from which all other ... View full abstract»

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  • Autonomous Clocks in Sequential Machines

    Publication Year: 1965, Page(s):467 - 472
    Cited by:  Papers (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1242 KB)

    A necessary and sufficient condition for the existence of an autonomous clock in a sequential machine M is found to be the existence of a nontrivial input-independent partition on the set of internal states of M, no matter whether M is completely specified or incompletely specified. Two different techniques are given for generating the smallest input-independent partition ¿I, from whic... View full abstract»

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  • Flow Table Simplification-Some Useful Aids

    Publication Year: 1965, Page(s):472 - 475
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (950 KB)

    Three results are presented pertinent to the problem of finding minimum-row versions of incompletely specified flow tables for sequential or iterative circuits. 1) Conditions are precisely stated under which preliminary mergers can be made without the danger of ruining opportunities for ultimately finding a minimal-row version. 2) A theorem by McCluskey is generalized to show that for all flow tab... View full abstract»

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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope