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Electronic Computers, IEEE Transactions on

Issue 3 • Date June 1965

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Displaying Results 1 - 25 of 54
  • [Front cover]

    Publication Year: 1965 , Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Group

    Publication Year: 1965 , Page(s): nil1
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    Freely Available from IEEE
  • Breaker Page

    Publication Year: 1965 , Page(s): nil1
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    Freely Available from IEEE
  • Enumeration of Seven-Argument Threshold Functions

    Publication Year: 1965 , Page(s): 315 - 325
    Cited by:  Papers (22)
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    A tabulation of the 2470 representative threshold functions of seven arguments has been prepared by the author. This paper discusses the methods used in, and the threshold logic implications of, the enumeration. The self-dual classification method of Goto-Takahasi was employed. A lattice was defined on the 8-cube in terms of which all 2-monotonic, canonical, self-dual functions of eight arguments were directly generated. Each such representative function was then treated by a modified form of the Muroga-Toda-Takasu linear programming test-synthesis procedure to obtain minimal 1-realizations. The Chow parameters for each function were calculated, and the final enumeration was ordered lexicographically by these parameters to afford a trivial test-synthesis procedure for n¿7. The enumeration demonstrated that minimal 1-realizations are still integral for n¿7; it corroborated Cobham's result that complete monotonicity is equivalent to 1-realizability, and established hyper-2-monotonicity as a useful characterization, for n¿7. It significantly extended our knowledge of the number of threshold functions and the various symmetry types, the size of weights and threshold required, the number of iterations required by the linear program, and similar statistics. View full abstract»

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  • Geometrical and Statistical Properties of Systems of Linear Inequalities with Applications in Pattern Recognition

    Publication Year: 1965 , Page(s): 326 - 334
    Cited by:  Papers (236)  |  Patents (1)
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    This paper develops the separating capacities of families of nonlinear decision surfaces by a direct application of a theorem in classical combinatorial geometry. It is shown that a family of surfaces having d degrees of freedom has a natural separating capacity of 2d pattern vectors, thus extending and unifying results of Winder and others on the pattern-separating capacity of hyperplanes. Applying these ideas to the vertices of a binary n-cube yields bounds on the number of spherically, quadratically, and, in general, nonlinearly separable Boolean functions of n variables. It is shown that the set of all surfaces which separate a dichotomy of an infinite, random, separable set of pattern vectors can be characterized, on the average, by a subset of only 2d extreme pattern vectors. In addition, the problem of generalizing the classifications on a labeled set of pattern points to the classification of a new point is defined, and it is found that the probability of ambiguous generalization is large unless the number of training patterns exceeds the capacity of the set of separating surfaces. View full abstract»

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  • Computing Irredundant Normal Forms from Abbreviated Presence Functions

    Publication Year: 1965 , Page(s): 335 - 342
    Cited by:  Papers (8)
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    A new method is presented for computing irredundant normal forms which renders feasible the handling of ``large'' functions. The method is based on the concept of abbreviated presence function and incorporates techniques found in the methods of ratio function and iterated consensus of the prime implicants. The complete set of irredundant normal equivalents of a formula is shown to be obtainable from an ``abbreviated presence function'' consisting of the presence relations corresponding to the prime implicants occurring in any one irredundant normal equivalent of the formula. Several examples are included to illustrate the economy in labor which the method provides. A new set of necessary and sufficient conditions is also given which allows a direct determination of absolutely dispensable prime implicants from the set of presence relations. The notion of absolute dispensability as presented here is related to that of Urbano and Mueller in which a prime implicant is absolutely dispensable if and only if it does not belong to an essential star. View full abstract»

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  • State Assignments in Combinational Networks

    Publication Year: 1965 , Page(s): 343 - 349
    Cited by:  Papers (3)
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    The problem of assigning codes to the output states of a multiple-output combinational circuit is considered. It is assumed that if the circuit has n inputs, then the 2n fundamental products, i.e., input states, are to be partitioned into disjoint groups, such that all members of the same group produce the same output state. The problem of coding the output states is studied here. Two algorithms for making the assignments are considered. The first gives those encodings for which the sum of the costs of all the output functions is minimum; the second minimizes the variable dependency of the output functions. In problems where reduced variable dependency is possible it has been found that the second algorithm yields minimum or near-minimum cost networks. Since this algorithm is easily applied it is useful for finding economical networks in situations where a large number of variables are involved since in such cases the first algorithm becomes lengthy. Attention is also directed to the problem of determining the optimum number of output variables to use for an encoding. An upper bound is derived and an example is presented which requires this bound. View full abstract»

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  • A Method for Minimizing the Number of Internal States in Incompletely Specified Sequential Networks

    Publication Year: 1965 , Page(s): 350 - 359
    Cited by:  Papers (83)
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    A method is illustrated for minimizing the number of internal states in incompletely specified sequential networks. The minimization algorithm applies to any type of incompletely specified flow table. It is shown that only some compatibility classes (prime compatibility classes) need be considered as members of a solution. The selection of prime classes may be obtained as the solution of an integer linear program or by tabular techniques that are an extension of those used in the selection of prime implicants. View full abstract»

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  • Synthesis of Error-Tolerant Counters Using Minimum Distance Three State Assignments

    Publication Year: 1965 , Page(s): 359 - 366
    Cited by:  Papers (11)
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    It is shown that by using minimum distance three state assignments and considering error states when deriving the input equations, counters tolerant of a single error can be synthesized. Although one flip-flop in the counter might be in error, the other flip-flops will continue to sequence correctly. Thus acceptable sequencing continues with a malfunctioning unit present in the circuit. Because of the error correcting properties of the state assignment, the correct state of the counter can be recovered. A one-bit error introduced by noise or an intermittent malfunction will be automatically corrected. Failure occurs if more than one flip-flop is in error. Redundancy is incorporated as an inherent result of the initial design procedure rather than being included after a nonredundant working design is obtained. Instead of using any of the known methods of simplification of Boolean functions, the synthesis procedure involves the selection of a minimum number of terms which satisfy a concise set of distance and intersection properties. The selection procedure is intrinsically suitable for machine computation. Although specific logic units are discussed, it is believed that the concepts are general in nature and can be applied to any type of logic hardware. View full abstract»

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  • Identification and Minimization of Linear Machines

    Publication Year: 1965 , Page(s): 367 - 376
    Cited by:  Papers (11)
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    This paper is a study of linear machines and their submachines. Methods are presented for finding the reduced form of a given linear machine with or without fixed initial state. A technique is suggested for detecting whether a machine is linear or can be embedded as a submachine in a linear machine. In the latter case a state assignment is produced for the minimum linear realization. Encoded inputs and outputs are assumed, but given machines are not assumed reduced, nor are there any restrictions on the number of states in the given machine or in the linear realization. The method also detects machines that are linearly realizable when constants are available. The main results are that the reduced form of a linear machine is linear and that a linearly realizable machine with r-independent states has an r-dimensional realization. View full abstract»

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  • Sequential Functions and Linear Sequential Machines

    Publication Year: 1965 , Page(s): 376 - 382
    Cited by:  Papers (1)
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    The``state'' of a sequential machine is interpreted as the sequence-to-sequence input-output mapping performed by the machine. Such mappings have been called sequential functions. This concept of state is applied to the theory of binary linear sequential machines. The modulo-2 adders are assumed to have an inherent delay td¿0, and the effects of initial conditions are considered. The pertinent results from the algebra of delay polynomials are summarized, and the state structure of linear sequential functions is outlined. It is shown that every retrospective linear sequential function can be realized using only unit-delay modulo-2 adders, and bounds are derived on the minimum realizable delay between input and output. View full abstract»

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  • Antiparallel Control Logic

    Publication Year: 1965 , Page(s): 383 - 393
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    This paper proposes a method, termed antiparallel control logic, for the control and efficient utilization of computer networks that exhibit substantial propagation delays on the lines interconnecting the logical elements, as well as in the elements themselves. The discussion encompasses the basic behavior of antiparallel stages that realize this method of control, including their logical realization and their extension to other useful network logic structures. In a strictly feedforward line, where the stored data are indexed forward by control pulses moving in a direction away from the data source, the existence of time variations in the delays of successive stages implies a nonzero probability that two successive control pulses will eventually appear at the inputs to a given stage so closely spaced that the basic reaction time of the stage is violated. The result is a failure of the transfer mechanism and a consequent loss of information. If feedback control is provided such that control pulses move in a direction opposite to the flow of information, that is, if the control and information flows are antiparallel, then the failure of the transfer mechanism does not cause an overlap in the information stored on the line, but rather leaves a void, or hole, which does not imply necessary information loss nor physically unrealizable storage requirements on the individual stages. View full abstract»

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  • A One-Dimensional Real-Time Iterative Multiplier

    Publication Year: 1965 , Page(s): 394 - 399
    Cited by:  Papers (20)  |  Patents (1)
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    The class of one-dimensional, real-time, iterative, discrete-state automata is described. By example, it is shown that serial multiplication can be carried out by such a sequential switching network. Each of two arbitrarily large integers is represented in binary notation by a time sequence of digits 0 or 1, the lowest order digits first. A design is given for a discrete-state machine that has as input the two time sequences of binary digits and as output a single sequence of binary digits, which is the product of the two input integers, lowest-order digit first. The multiplier is constrained to be a linear array of identical cells. The cells each have a finite number of states and each cell communicates directly only with the adjacent cells, such communications occurring in a synchronous manner. The multiplication is performed in real time; that is, the delay between the receipt of the nth digits of the input and the generation of the nth digit of the output is a fixed number of periods of the synchronizing clock. A design with no time delay is described. View full abstract»

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  • ILLIAC II-A Short Description and Annotated Bibliography

    Publication Year: 1965 , Page(s): 399 - 403
    Cited by:  Papers (1)
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    ILLIAC II is a general purpose computer built at the University of Illinois, Urbana. It contains about 55000 transistors and has a floating multiply time of 6.3 μs. A number of features are provided to increase the speed of operation. There are three controls in largely concurrent operation. The control circuits are largely asynchronous and speed independent. The floating point arithmetic unit contains two adders and utilizes redundant number representation and separate carry storage. The memory hierarchy has members ranging from the 10-word, 0.2-μs. flow gating memory to magnetic tapes. Order fetches from the main 1.8-μs. core memory are minimized by packing two to four orders per word, and by holding two words of orders in the flow gating memory for execution of short loops. The bibliography lists 40 papers related to the design of this computer. View full abstract»

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  • LOCS: An EDP Machine Logic and Control Simulator

    Publication Year: 1965 , Page(s): 403 - 416
    Cited by:  Papers (3)  |  Patents (1)
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    The new EDP Machine Logic and Control Simulator, LOCS, is designed to facilitate the simulation of data processing systems and logic on the IBM 7090 Data Processing System. With this simulator, it will be possible to operate and execute commands in a manner comparable to that of a hardware version of the machine being simulated. The inputs to LOCS consist of a description, coded in LOCS language, of the machine to be simulated and a set of test programs coded in either the procedure language of the test problems (e.g., FORTRAN), or in the instruction language of the simulated machine. If a procedure language is used, a suitable translator program coded in machine language must be included to translate the test programs into machine code. The outputs of LOGS consist of the performance statistics, computation results, and diagnostic data which are relevant to both the test programs and the design of the simulated machine. This paper first describes the LOCS System including a description of LOCS inputs and outputs as well as an outline of the procedure one must follow to use LOCS. Next, the method of using LOCS is illustrated by an example of the complete simulation of a simple conventional binary data processing machine; and following this, a summary of current status. View full abstract»

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  • Direct Execution of Programs in Floating Code by Address Interpretation

    Publication Year: 1965 , Page(s): 417 - 422
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    This paper describes the use of a very high-speed scratch pad memory for directly executing programs in floating code with a single origin or multiple origins. When a program is being loaded into the magnetic core memory of a digital computer, there is no need of modifying the addresses of the original code. Neither the programmer, nor the operator, nor the program loader has to know where are the available locations in the magnetic core memory. During the subsequent execution of the program, the logical and physical correspondence of the addresses of the code is found by hardware address interpretation. The operations involved in address interpretation are described as well as the organization and control sequence of the computer. The use of the scratch pad memory can also be extended for dynamic allocation of magnetic-core memory locations and for memory protection of all programs which do not have to lie in physically contiguous areas of the memory. View full abstract»

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  • A Versatile Comparator for Encoding Devices

    Publication Year: 1965 , Page(s): 423 - 427
    Cited by:  Papers (1)
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    The complexity, speed, and accuracy of encoding systems depend strongly upon the type of voltage amplitude comparator used. Encoding techniques such as successive approximation and time base use only a single comparator while parallel encoding and nonprogrammed feedback encoding require at least one comparator for each stage. This paper presents a versatile voltage amplitude comparator with suggestions for its use in all basic encoder types and with design procedures which will provide increased voltage sensitivity. To indicate further the use of the comparator, a three-bit encoder design is presented. View full abstract»

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  • Fixed Resistor-Card Memory

    Publication Year: 1965 , Page(s): 428 - 434
    Cited by:  Papers (1)
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    A fixed or read-only memory, consisting of a stack of paper or plastic punched cards, each containing an interconnected array of printed resistors, is discussed. The cards are compatible with conventional keypunches, and information is recorded on each card by the punching of a pattern of holes, each of which severs an appropriate connection. An interconnection method, which involves the injection of molten, low-temperature solder alloy into special channels in the stack, is described. This technique provides all card- to-card interconnections simultaneously. It is shown that the memory can be operated in a content-addressable or associative mode. Experimental results, dealing with resistor silk-screening and card stack construction and operation, are presented. View full abstract»

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  • A Parapropagation Pattern Classifier

    Publication Year: 1965 , Page(s): 434 - 443
    Cited by:  Papers (5)
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    A matrix of simple, identical intercommunicating cells is the core of a pattern classifier that can sort two-valued, two-dimensional patterns, such as alphabetic symbols. The matrix yields information about a patterm mapped on its cells by reporting whether or not a threshold exceeds the number of cells that remain in a ``zero'' state after a sequence of operations that include directed cell-to-cell propagations of change of state. The pattern furnishes a barrier to the propagations. The testing process is a program written to suit some alphabet of pattern classes. An automatic sequencer for controlling the testing process is described. The testing operations are few, but they can be combined in tests for an abundance of features of great variety. A computer simulation, using a single decision tree, classifies the commonest press and typewriter fonts. A small manually sequenced model employing integrated microelectronic cells has been built. View full abstract»

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  • Acoustic Ray Tracing on the General-Purpose Electronic-Analog Computer

    Publication Year: 1965 , Page(s): 443 - 455
    Cited by:  Papers (1)  |  Patents (1)
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    A simulation of the trajectory of underwater acoustic rays is implemented on a general-purpose electronic-analog computer. Equations defining the phenomena are summarized, assumptions are listed, and a preferred form of the equations is developed to provide maximum attainable accuracy of solution. Included are considerations of the velocity of sound as an arbitrary function of both depth and range, and the effects of reflections from both the surface and an arbitrary bottom. A complete computer diagram is presented and special circuits are described. Typical results of depth versus range are shown for varying launch depths and launch angles. A method of obtaining the difference in time required for rays leaving a common emitter at various angles to reach a common receiver is also derived. By use of perturbations, Taylor series expansions, and the method of steepest descents to insert the constraint cos ¿/c = constant, the overall error in this highly sensitive computation has been reduced to 0.01 per cent or better. View full abstract»

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  • Optimum Design of a Diode Squarer by Applying the Criterion of Square Root of the Integral of Per Cent Error Squared

    Publication Year: 1965 , Page(s): 456 - 463
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    Quarter-square diode analog multipliers are composed of two diode squaring channels. The selection of the diode breakpoints and the output level at each of them involves essentially the optimization of a straight-line segment approximation to the ideal parabolic output. This optimization has often been discussed and actually carried out in commercial multipliers using the least value of the integral of squared error as the optimization criterion. This and other published criteria, however, focus on smoothing the error, but allow a large per cent error in the region of small input. To smooth the per cent error over the whole range a new criterion of the square root of the integral of per cent error squared was applied. The design was carried out on a computer using a type of dynamic programming search process which allowed easy experimentation with the criterion as well as the easy incorporation of practical design requirements. The resulting design showed a substantially smoother per cent error over the entire range with only a very slight increase in per cent error in the region of higher inputs. View full abstract»

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  • On the Bound to the Memory of a Sequential Machine

    Publication Year: 1965 , Page(s): 464 - 466
    Cited by:  Papers (7)
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    Following Moore [1], consider a sequential machine (discrete, synchronius automata) having n states or less, m inputs, and p-possible outputs. The state that the machine is in at a given time depends only on the state at the previous time and the previous input. The output at a given time depends only on the current state. In addition the machine is strongly connected. That is to say, it is possible to take it from any state to any other state by means of some sequence of inputs. Finally, the machine is in reduced form, which may be taken to mean that it is not possible to design a sequential machine having fewer states whose behavior, in so far as its inputs and outputs are concerned, is identical with the behavior of the original machine. As a gedanken experiment, one may attempt to determine the table of state transitions and outputs of this machine (to within a renaming of its states) by applying inputs and observing the corresponding outputs. It is assumed that one does not just open up the machine and trace its circuits. What will be the length of this gedanken experiment? That is, how many inputs are needed? View full abstract»

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  • An Improvement on a Theorem of E. F. Moore

    Publication Year: 1965 , Page(s): 466 - 467
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    A necessary and sufficient condition for the existence of an autonomous clock in a sequential machine M is found to be the existence of a nontrivial input-independent partition on the set of internal states of M, no matter whether M is completely specified or incompletely specified. Two different techniques are given for generating the smallest input-independent partition ¿, from which all other input-independent partitions can be obtained. One is suitable for a sequential machine whose state behavior is specified in the form of a flow table, while the other is convenient for a sequential machine whose state behavior is specified in the form of a connection matrix. Both techniques are efficient, and give all possible assignments to the redundant conditions of an incompletely specified sequential machine to reach the same nontrival input-independent partition, and hence the same autonomous clock. View full abstract»

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  • Autonomous Clocks in Sequential Machines

    Publication Year: 1965 , Page(s): 467 - 472
    Cited by:  Papers (2)
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    A necessary and sufficient condition for the existence of an autonomous clock in a sequential machine M is found to be the existence of a nontrivial input-independent partition on the set of internal states of M, no matter whether M is completely specified or incompletely specified. Two different techniques are given for generating the smallest input-independent partition ¿I, from which all other input-independent partitions can be obtained. One is suitable for a sequential machine whose state behavior is specified in the form of a flow table, while the other is convenient for a sequential machine whose state behavior is specified in the form of a connection matrix. Both techniques are efficient, and give all possible assignments to the redundant conditions of an incompletely specified sequential machine to reach the same nontrival input-independent partition, and hence the same autonomous clock. View full abstract»

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  • Flow Table Simplification-Some Useful Aids

    Publication Year: 1965 , Page(s): 472 - 475
    Cited by:  Papers (14)
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    Three results are presented pertinent to the problem of finding minimum-row versions of incompletely specified flow tables for sequential or iterative circuits. 1) Conditions are precisely stated under which preliminary mergers can be made without the danger of ruining opportunities for ultimately finding a minimal-row version. 2) A theorem by McCluskey is generalized to show that for all flow tables if optional entries arise only due to restrictions as to which input states may immediately follow one another, then the reduction problem is relatively simple. 3) A useful heuristic in the form of a diagram illustrating implication relations of 2-member compatibles is introduced as an aid in finding minimal closed sets of compatibles. View full abstract»

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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope