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Electronic Computers, IEEE Transactions on

Issue 2 • Date April 1965

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Displaying Results 1 - 25 of 58
  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Group

    Page(s): nil1
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    Freely Available from IEEE
  • [Breaker page]

    Page(s): nil1
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    Freely Available from IEEE
  • [Breaker page]

    Page(s): nil2
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    Freely Available from IEEE
  • New Associate Editor for Analog and Hybrid Computers

    Page(s): 123
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    Freely Available from IEEE
  • Generation and Asymmetry of Self-Dual Threshold Functions

    Page(s): 125 - 136
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    Properties of self-dual threshold functions are discussed because of the importance of self-dual functions in threshold logic. Since any threshold function can be easily converted into or reduced from a positive self-dual threshold function, we will not lose generality in discussion by exploring the properties of positive self-dual threshold functions. First functions generated by additively or subtractively merging two variables of a positive self-dual threshold function are discussed. Expansions of a positive self-dual threshold function with respect to two variables are then shown, and the generation of functions based on them is discussed. The concepts of strongly asymmetrical selfdual threshold functions and its degree are introduced, and the relation of all self-dual threshold functions of fewer variables with strongly asymmetrical ones is shown. The above discussion enables the classification of threshold functions and the relation between threshold functions of n variables and those of more variables to be better seen. View full abstract»

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  • Lower Bounds of the Number of Threshold Functions and a Maximum Weight

    Page(s): 136 - 148
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    A lower bound on the number of threshold functions and a lower bound on the maximum of minimum weights of a threshold element are derived from a recursively constructed family of threshold elements. All threshold functions of n variables are difficult to construct for a general value of n, but it is shown that a large number of them can be constructed recursively from threshold functions of fewer variables. Schemes of such generation and related proper ties are discussed. Threshold functions generated in this way are so numerous that they constitute a constructive proof of a good lower bound on the number of threshold functions. By a similar procedure, we can derive a lower bound on the maximum of minimum weights of a threshold element. In this paper, discussion is limited to self-dual threshold functions, but this does not sacrifice generality, because any threshold function can be derived from a self-dual threshold function by assigning 1 or 0 to a certain variable. View full abstract»

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  • Regular Expressions for Linear Sequential Circuits

    Page(s): 148 - 156
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    This paper considers the class of linear sequential circuits from the regular expression point of view. The circuits studied do not have special starting units which are necessary in the conventional construction of circuits from regular expressions. Since conventional regular expressions are only indirectly related to the circuit structure, a new regular language is developed. Using this language, the regular expression accepted by a linear circuit can be obtained more directly from the circuit. The regular expressions are then interpreted to provide a word description of the circuit behavior. View full abstract»

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  • Completeness of Sets of Delayed-Logic Devices

    Page(s): 157 - 172
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    This paper concerns a property of sets of delayed-logic devices. This property, called completeness, characterizes sets of logic devices that can be used for the construction of networks to represent any finite-state machine. Associated with this property is a rate of completeness, which is the maximum input sequence rate for which any finite-state machine can be constructed from the given set of devices. Tests for completeness are presented from which the completeness or lack thereof may be determined for certain classes of sets of devices. For complete sets of devices, these tests also determine the rate of completeness. View full abstract»

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  • On Complete Sets of Logic Primitives

    Page(s): 173 - 174
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    A complete set of logic primitives is a set of devices which can be connected to represent any Boolean function of binary variables. This paper deals with the number of devices required in a complete set of logic primitives. It is well known that a complete set of logic primitives may contain as few as one element, e.g., NOR. It is the purpose of this paper to establish a least upper bound on the number of nonredundant elements in a complete set. It is shown that every complete set contains a complete subset with at most four elements. Further, a complete set with four elements is presented which is incomplete if any element is deleted. View full abstract»

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  • A Diagrammatic Approach to Multilevel Logic Synthesis

    Page(s): 174 - 181
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    A diagrammatic approach to the problem of synthesizing multilevel logic functions is presented. It has the advantage of giving a visual interpretation to such abstract concepts as fan-in, levels of logic, decomposition, and two-level forms. View full abstract»

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  • Minimal Square Rooting

    Page(s): 181 - 185
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    Binary square rooting algorithms which yield a root in a redundant representation using digits 1, ¿1, and 0 are analyzed, particularly those yielding a root in a representation in which the number of nonzero digits is minimal. An algorithm which may lead to any possible minimal representation of the square root is developed. View full abstract»

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  • Bulk Processing in Distributed Logic Memory

    Page(s): 186 - 196
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    Use of a content-addressable memory as a highly parallel digital computer is described. The ability to perform any arithmetic operation on many sets of data at the same time is shown. The memory organization and the storage of data are such that many operations are performed parallel by bit as well as parallel by word, resulting in more efficient algorithms and shorter execution times. Consideration of the limitations of a linear memory array in performing such operations leads to the description of a more efficient organization, called the two-dimensional distributed logic memory. The efficiency of this form in the bulk processing of data is illustrated by a number of algorithms for basic data processing operations, including matrix inversion. View full abstract»

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  • A Magnetically Scanned Magnetic Tape Transducer

    Page(s): 196 - 203
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    A new digital magnetic tape transducer intended to provide megabit per second data transfer speeds with moderate tape speed is described. This magnetic tape transducer contains no moving parts, but records on the tape along transverse tracks. Sweep of the effective or operative area of the transducer across the tape is accomplished by selectively controlling the permeability of one of the magnetic members. A large portion of this transducer is fabricated from thin magnetic films deposited upon glass substrates. The performance of the transducer is determined to a large extent by the magnetic switching characteristics of one of these thin films. The magnetic properties required of these films are derived in terms of the desired frequency response. The impulse response is calculated partially taking into account the nonlinearity of the tape but neglecting demagnetization effects. As an aid to making design choices, the frequency response of the transducer is computed from the impulse response. The magnetic parameters, the dimensions of the transducer and tape, and the speed of the sweep across the tape are chosen to obtain a frequency response of about 4 Mc/s. The experimentally obserrved pulse response using prerecorded tape compares favorably with the predicted impulse response. However, considerable playback noise which is probably associated with the thin magnetic films has been observed. It appears that an extensive material development would be required before this transducer could be utilized. View full abstract»

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  • Linear, Passive, Matched Filter for Digital Magnetic Recording

    Page(s): 204 - 209
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    A linear, passive matched filter is developed for the readback portion of digital magnetic recording systems. The filter, by maximizing the signal-to-noise ratio (SNR), improves the reliability of digital magnetic recording. This is necessary because the continuous improvement in magnetic recording resolution has brought about a consequent deterioration in the SNR. For the worst case, namely, when the signal and noise occupy precisely the same band of frequencies, laboratory experiments show an improvement factor of 3.42 in the SNR. The filter tested was of very low cost since it was built with standard off-the-shelf components. It can be easily implemented in any given situation by simple network scaling. View full abstract»

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  • Computer Recognition of Handwritten First Names

    Page(s): 210 - 217
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    Alearning program incorporating a version of stimulus-sampling theory was prepared for a digital computer. Handwritten first name signatures coded in a 20 by 48 grid served as inputs to study the effects of parameter changes in the program. Under one main condition the computer with its program examined only those grid cells in which any part of a given pattern fell. Under a second main condition each of the 960 grid cells was examined. Learning of correct pattern names occurred under both conditions. The level of learning achieved under the second condition was higher, although the improvement was gained at the expense of considerably extended running times. View full abstract»

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  • Economical Circuits for the Analog Solution of Algebraic Equations

    Page(s): 217 - 229
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    The only methods previously available for the design of stable analog circuits for the solution of algebraic equations involved extensive preparatory calculations or the use of an excessive number of amplifiers. This paper examines the causes of instability and gives a method which enables a stable circuit using the minimum of equipment to be designed for any nonsingular set of algebraic equations. The method is ideal for the design of high-speed circuits. View full abstract»

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  • Frequency Analysis of Truncation Errors in RC Networks

    Page(s): 229 - 233
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    This paper provides guidelines for the discretizing of the space variables in continuous systems governed by the second-order partial differential diffusion equation. Such lumping is necessary in all digital and many analog methods. To analyze the truncation error resulting from lumped analog or digital modelling, the authors demonstrate the applicability of an upper-bound criterion combining amplitude and phase errors in the frequency domain. Dimensionless variables are used to compare lumped networks corresponding to one-dimensional continuous systems. Computer results are presented which relate truncation error to frequency for lumped models containing one to ten sections. View full abstract»

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  • On Using an Analog Computer to Study Hydrodynamic Stability

    Page(s): 233 - 238
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    The use of analog computers to study hydrodynamic stability is complicated by the fact that the governing differential equation has two rapidly varying solutions (one growing and one decaying), and two which are well behaved. Thus, errors in setting initial conditions and noise in an analog computer excite the rapidly growing solution, making the computer behave in an unstable way. This unstable behavior has its origin in the role played by fluid viscosity. Approximate techniques are discussed whereby these instabilites can be circumvented. The techniques are applied to the case of the Blasius boundary layer on a flat plate, and the results are compared with results available in the literature, obtained with a digital computer. The analog-and digital-computer results are in good agreement. View full abstract»

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  • Improved Methods of Simulating Time Delays

    Page(s): 239 - 243
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    A new group of time-delay polynomial approximations are obtained by trial and error methods. The results of the trial and error procedure suggest an analytic method for finding the new approsimations. The new approximations and their usable bandwidths are tabulated for second-through sixth-order polynomials. Delay vs. frequency graphs of the fourth-and fifth-order polynomials are compared with several previously published approximations. Also methods are suggested for delaying short signals and step functions for long periods. View full abstract»

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  • The Cascade Multiplier

    Page(s): 243 - 247
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    A new principle and circuit for the generation of the product of two variables is described in which the required result is a linear combination of readily produced secondary variables. The product of two variables can be expanded in a series in which each term is derived from the preceding one and from an auxiliary variable by linear operations and by maximum and minimum selection. Two ``converted'' variables are associated with each term of the expansion. The product is equal to a linear combination of the converted variables plus the product of the last two converted variables. The range of variation of successive converted signals decreases by half so that the series converges by factors of ¿ per term. The exrpansion stands in direct correspondence with electronic multipliers which use linear elements and diode selection circuits. Only two sign-changers are required for four-quadrant operation. When used in conjunction with an ancillary four-quadrant multiplier, the cascade multiplier increases its accuracy by factors of 4, 16, 64,..., if 1, 2, 3, ..., stages are used. Alternatively, a sufficient number of stages provides a complete multiplier even without the use of an ancillary multiplier. Accuracies of the order of ±0.1 per cent are readily obtained and speed of response is high. View full abstract»

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  • Correction [to "An approach to single-threshold-element synthesis"]

    Page(s): 247
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    M.L. Dertouzos, author of the paper "An Approach to Single-Threshold-Element Synthesis," which appeared on pp. 519-528 of the October, 1964, issue of these Transactions has called the following corrections to the attention of the Editor. On page 520, (3), the summation endpoints are corrected; on page 523, following (21), the equation is corrected; on page 525, the expression for Theorem 2 is corrected. View full abstract»

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  • A Ternary Storage Element Using a Conventional Ferrite Core

    Page(s): 248
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    A new group of time-delay polynomial approximations are obtained by trial and error methods. The results of the trial and error procedure suggest an analytic method for finding the new approximations. The new approximations and their usable bandwidths are tabulated for second-through sixth-order polynomials. Delay vs. frequency graphs of the fourth-and fifth-order polynomials are compared with several previously published approximations. View full abstract»

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  • Using a Decision-Table Structure as the Input Language Format for Programming Automatic Test Equipment Systems

    Page(s): 248 - 250
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    Compiler programs are used to convert engineering test specifications to a digital code which can be interpreted by the automatic test equipment system. A programming language based upon decisiontable techniques allows the test engineer to write his test statements in an extremely convenient fashion and permits him to program any test specification with only a minimum of knowledge about the specific test equipment system and particular programming techniques. View full abstract»

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  • Chebyshev Approximation and Threshold Functions

    Page(s): 250 - 252
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    Where previous authors have considered linear approximations with a minimum sum of squared differences, we consider, instead, Chehyshev linear approximations, which minimize the maximum deviation. We obtain thus: 1) A new characterization of threshold functions, 2) A characterization of optimal threshold realizations as being virtually identical to the Chebyshev-best linear approximations, and 3) A new insight into the test-synthesis problem with which we opened this note. View full abstract»

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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope