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Electronic Computers, IEEE Transactions on

Issue 6 • Date Dec. 1964

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Displaying Results 1 - 25 of 42
  • [Front cover]

    Page(s): c1
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  • IEEE Computer Group

    Page(s): nil1
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  • Breaker Page

    Page(s): nil1
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  • On the Linearity of Autonomous Sequential Machines

    Page(s): 673 - 679
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    This paper presents a method of determining, from the flow table of an autonomous sequential machine, whether the machine can be realized by a linear circuit which uses the minimum possible number of secondary variables. The method is based on a class of binary partitions of states, which are used to find a minimal assignment of the secondary variables such that the next state and output functions are linear. The partitions are examined in detail and the properties necessary to produce a valid assignment are developed. View full abstract»

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  • Properties and Transformations of Single Threshold Element Functions

    Page(s): 680 - 684
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    A large number of Boolean functions may be realized as the output of a single threshold element; however, not all functions are so realizable. Those Fn which are, are said to belong to the class R. No easily applicable criteria have been formulated which enable an unequivocal determination to be made of whether a given Fn¿ R. There are, however, certain transformations allowable on those Fn¿ R which exhibit a closure property, that is, the transformation results in an Fp¿ R. There are also certain properties of the form of Fn¿ R which can be recognized easily. A knowledge of these permissible transformations and observations of the form of a given Fn will, in many instances, allow for the desired. determination. This paper, for the most part, examines those permissible transformations and properties of form. View full abstract»

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  • Cutpoint Cellular Logic

    Page(s): 685 - 698
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    A cutpoint cellular array is a two-dimensional rectangular arrangement of square cells, each of which has binary inputs on the top and left edges and outputs on the bottom and right edges. Each cell is interconnected with neighboring cells, and it is specialized by a set of binary constants that are termed cutpoints. This paper is concerned with the choice of the logical properties for each cutpoint cell, so that an array of these cells is capable of efficient and general combinational and sequential logic. Logical design algorithms are given, as well as a number of actual designs. It is believed that cutpoint cellular arrays have promise for application in the manufacture of a large number of integrated circuit components on one substrate. View full abstract»

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  • Decompositions of Logical Functions Using Majority Decision Elements

    Page(s): 698 - 705
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    A method of decomposing logical functions using three input majority gates is given. This method requires that at least one of the inputs to the gate be specified, and from this the other inputs may be found. For unate functions one of the variables may be completely separated at each level. A method using a Karnaugh map is proposed for finding the best function to use as the specified input, which will make the other inputs to the majority gate easier to synthesize. View full abstract»

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  • Mathematical Models for Predicting Pulse Characteristics in Digital Logic Systems

    Page(s): 705 - 710
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    The multiple use of a relatively few types of basic building blocks in digital computers requires that the system designer know the actual performance characteristics of these units in order to produce optimum designs. Worst-case analysis procedures do not yield realistic performance data. The performance-prediction technique discussed in this paper is based on the development of empirical mathematical models which relate the performance variables of interest to the pertinent system parameters. Prediction equations are fitted for the logic elements in a parity-check network for rise, fall, delay, and storage times as a function of the fan-in and fan-out of the logic element and the fan-in and fan-out of the stages which drive it. A statistical analysis of the prediction equations is made to determine the validity of the models. The goodness of fit of these models is presented in graphical form. View full abstract»

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  • Design for a Tunnel Diode-Transistor Store with Nondestructive Read-Out of Information

    Page(s): 710 - 722
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    The design of a random-access, word-organized storage system with nondestructive read-out of information is described. The storage element upon which the design is based consists of a tunnel diode-transistor combination. Measurements on a simulated store of 16 words ×24 digits capacity indicate that cycle times of approximately 40 nsec for Read orders and 65 nsec for Write orders can be achieved. View full abstract»

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  • Amplifier and Driver Circuits for Thin Film Memories with 15 Nanoseconds Read Cycle Time

    Page(s): 722 - 729
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    Amplifier and driver circuit design principles for an experimental 4608-bit nondestructive thin film memory with 13.5-nsec read and 60-nsec write cycle times are given. The bit noise problems inherent in the common bit sense line concept are solved by using tunnel diodes in a nonlinear balancing circuit. A further improvement of the signal-to-noise ratio is achieved by employing a noise resistant sense amplifier with nonlinear negative feedback. The word driver described is capable of delivering 700 ma pulse amplitude at 50 mc repetition rate at a pulse width of 7 nsec. View full abstract»

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  • Computer-Aided Digital System Design and Analysis Using a Register Transfer Language

    Page(s): 730 - 737
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    This paper presents the results of an attempt to automate part of a formalized method of system design. Basic to this method are two languages, Boolean algebra and a register transfer language. From a Boolean algebra description a digital system can be constructed while the second language can be used in a step by step description of the execution of each instruction. To illustrate, a register transfer language is used to give a description of an adder considered as part of a digital system. This description is then translated into a set of Boolean equations. Next, the automation of this translation by using a syntax-directed compiler is explained. The compiler requires a syntactic description of register transfers. This description is given using a meta-language called Backus normal form. A Backus normal form description of Boolean equations that is used for translating Boolean equations into register transfers is also given; this translation process is called analysis. The feasibility of computer-aided design and analysis is thereby demonstrated. The computer-aided design method described in this paper, besides eliminating drudgery and error, would permit several system designs to be attempted and evaluated; a permanent record of the chosen system would also be available for future modifications, maintenance, and simulation. The analysis programs could be used to check the effect on the system of any changes made in the Boolean equations (or equivalently the logical diagrams) and the effect of any unused operation codes. View full abstract»

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  • Rational Numbers and Regular Events

    Page(s): 740 - 741
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    In this paper the relation between a sequential circuit and its regular expression is investigated. The circuits are without special starting units. One method of analysis of a circuit leads to a set of equations whose solutions are regular expressions related to the state diagram of the circuit. In another approach, a set of regular equations, identical in form to the next state equations, is obtained directly from the circuit. By reversing the regular equations and using derivatives, the regular equations are transformed to a form related to the reverse state diagram. The discussion clarifies the relationship among circuits, regular expressions and state diagrams. Moreover, further insight is obtained into the solution of equations with as unknowns. View full abstract»

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  • Regular Expressions from Sequential Circuits

    Page(s): 741 - 744
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    In this paper the relation between a sequential circuit and its regular expression is investigated. The circuits are without special starting units. One method of analysis of a circuit leads to a set of equations whose solutions are regular expressions related to the state diagram of the circuit. In another approach, a set of regular equations, identical in form to the next state equations, is obtained directly from the circuit. By reversing the regular equations and using derivatives, the regular equations are transformed to a form related to the reverse state diagram. The discussion clarifies the relationship among circuits, regular expressions and state diagrams. Moreover, further insight is obtained into the solution of equations with regular expressions as unknowns. View full abstract»

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  • A Digital Decoding Technique

    Page(s): 745 - 746
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    In the course of the design of a small-scale digital computer for use as a communications buffer and processor it was found possible to greatly increase the capability of the computer in the encoding and decoding of a number of error control codes without significantly increasing the complexity of the hardware by the addition of three commands to the instruction repertoire of the computer. These commands are Galois Field Multiply, Galois Field Divide, and Compute Word Parity. View full abstract»

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  • Simple Instructions Which Enhance the Error Control Capabilities of a Programmed Communications Processor

    Page(s): 747 - 748
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    In the course of the design of a small-scale digital computer for use as a communications buffer and processor it was found possible to greatly increase the capability of the computer in the encoding and decoding of a number of error control codes without significantly increasing the complexity of the hardware by the addition of three commands to the instruction repertoire of the computer. These commands are Galois Field Multiply, Galois Field Divide, and Compute Word Parity. View full abstract»

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  • Some Further Experiments in the Parallel Processing of Pictures

    Page(s): 748 - 750
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    While considerable attention has been devoted to the problems of automatic character recognition, either handwritten or printed, almost all such work has involved static examination of the characters. Little attention'12 has been paid to techniques for dynamic character recognition, i.e., examination during the time of formation, presumably because such processes have tended to be inefficient as communication techniques and wasteful of computer time. With the recent interest in closer man-machine coupling3 and the development of computer time-sharing techniques' to make such coupling economic, it is important to consider ways to utilize manual printing as a link to a computer system, particularly since the size and nature of the character sets available on convention keyboards is restricted compared to the symbol requirements in many disciplines. For example, it would be very useful to be able to describe a mathematic expression to a FORTRAN compiler using normal mathematical forms including integral signs, etc. View full abstract»

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  • Contributors

    Page(s): 755 - 756
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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope