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Electronic Computers, IEEE Transactions on

Issue 3 • Date June 1964

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Displaying Results 1 - 25 of 53
  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • IEEE Computer Group

    Page(s): nil1
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    Freely Available from IEEE
  • [Breaker page]

    Page(s): nil1
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  • Keith W. Uncapher New Chairman of the IEEE Computer Group

    Page(s): 183
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  • Message from the New Chairman

    Page(s): 184
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  • New Officers and Members of the Board

    Page(s): 185 - 192
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  • Secondary State Assignment for Sequential Machines

    Page(s): 193 - 203
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    One of the most important and complicated problems in the synthesis of a sequential machine described by a state diagram or table is the assignment of the states of the secondary variables to the states of the machine. The secondary assignment for a given machine varies in accordance with the requirements of the design. It has already been shown that the partition with the substitution property and the partition pairs are of great significance in the secondary assignment. However, only few machines possess these properties, and hence, a more general method is needed. This paper presents a method of obtaining for any given machine M an equivalent machine M¿ which has a partition with the substitution property or partition pairs and therefore can be decomposed into two or more submachines connected in cascade or possibly in parallel. It is also shown that for machine M¿ we can find an assignment with self-dependent subsets. The method is shown to be general for any completely or incompletely specified sequential machine. View full abstract»

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  • On the Convergence and Ultimate Reliability of Iterated Neural Nets

    Page(s): 204 - 225
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    The organization and reliability of large redundant nets of formal neurons are investigated. Each neuron has m inputs and n outputs and is capable of performing at any one time any member of any prescribed subset of the total possible set of 22m·n functions. Various methods for obtaining large nets of predictable structure and function through the medium of element reproduction are discussed. In the principal reproduction scheme considered, called ``complete iteration,'' each element ``grows'' a copy of the net of which it is a part and each new element does likewise, ad infinitum. The output or net function is studied as the number of ``iterations'' or ``reproductions'' increases. The concept of net convergence (or oscillation) which is equivalent to the condition achieved by the net when its set of net functions becomes stable (or oscillatory) is precisely defined. Theorems are proved which predict this behavior for various nets of general interest. A polynomial system is associated with each net which completely describes its probabilistic behavior. This system produces the Moore-Shannon h(p) function in the special case where the net stabilizes (converges) on only two functions. Conditions are given under which a net may be made arbitrarily reliable even though its constituent elements are arbitrarily unreliable. View full abstract»

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  • Analysis of Linear Sequential Circuits by Confluence Sets

    Page(s): 226 - 231
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    In this paper the group-theoretical concept of ``confluence sets'' is introduced as a valuable tool in the analysis of linear sequential circuits (LSC's). Using this concept, a scheme is formulated for producing state graphs of autonomous LSC's which, in the ``singular'' case, is superior to currently known schemes. Singular LSC's, which are of potential interest in error correction systems, are studied in detail. Properties of their state graphs are derived, culminating in a unique characterization of such graphs in terms of representative ``cycles'' and ``trees.'' Together with known results on nonsingular circuits, the results in this paper offer a description of the autonomous behavior of the general linear sequential circuit. View full abstract»

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  • A Method for Testing and Realization of Threshold Functions

    Page(s): 232 - 239
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    A standard method for testing and realizing a threshold function is to solve a set of linear inequalities in which the unknowns are the n weights to be assigned to the n variables. In this paper a simple method of solving this set of inequalities is presented. Instead of using the weights themselves as the unknowns, a set of n new unknowns, the incremental weights ¿a1, ¿a2, . . ., ¿an¿1, together with the lowest weight an, is used. This change of unknowns results in a simpler set of inequalities which, in turn, furnishes direct information on 1-realizability1 of the function and on the assignment of weights for realization, often without the necessity for trial and adjustment. View full abstract»

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  • DONUT: A Threshold Gate Computer

    Page(s): 240 - 247
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    During the past few years there has been a considerable amount of literature concerned with the realization of threshold logic. However, there are a number of questions concerning such factors as sensitivity and component savings which cannot be completely answered by such theoretical studies. DONUT (Digitally Operated Network Using Thresholds) is a small general purpose digital computer which was designed and constructed to evaluate the feasibility of using threshold gates as the basic logical element. Exclusive of memory the computer consists of about 500 threshold gates. The design was carried out for five different values of component tolerances and the tightest tolerance version was constructed. Component savings for the constructed machine are about a factor of four compared with the loosest tolerance NOR gate realization. Experiments were made to verify that the power supply and logical voltages were within tolerances in the system environment. View full abstract»

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  • The CSX-l Computer

    Page(s): 247 - 250
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    A brief description of the logical structure and the instruction repertoire of a short word length (16 bits) computer is given. The unorthodox features which are discussed are 1) a variable-length addressing procedure, 2) a common multi-accumulator and index register structure, and 3) the identical processing of data and addresses. View full abstract»

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  • A Quantising Encoder

    Page(s): 250 - 254
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    A device is described that converts voltages to digital form by means of a strategy basically faster than that used in the conventional trial encoder. A voltage corresponding to the contents of a 2n-bit register is obtained from the output of the digital-voltage decoder. The error between this voltage and the input voltage is quantized to the nearest power of two and subtracted from the contents of the register. Each time this process is repeated, the error is diminished. In all, n repetitions of the process are required to complete the encoding. An encoder operating according to this strategy has been built and makes a complete 8-bit conversion in 4, ¿sec. View full abstract»

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  • High-Density Binary Recording Using Nonsaturation Techniques

    Page(s): 255 - 261
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    Commercially available magnetic tape units have longitudinal recording densities of up to 2000 bits per inch, whereas analog instrumentation recorders are capable of recording up to 10,000 cycles per inch. These figures contrast with a theoretical recording density limitation for iron oxide of 250,000 bits per inch, and the reasons for this discrepancy are analyzed. Two experimental systems having recording densities of 5000 and 10,000 bits per inch using analog recording techniques are described, Conclusions drawn from these experiments indicate that a density of 20,000 bits per inch should be possible using commercially available analog tape recording machines. Experimental machines indicate the practicability of densities on the order of 100,000 to 200,000 bits per inch, depending on the method of recording used. View full abstract»

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  • Cylindrical Film Memory Device Characteristics

    Page(s): 261 - 268
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    This device is a single-bit storage element consisting of a 100-mil piece of 25-mil glass tubing with a 6000-A nickel-iron film coating. This paper describes those properties of the device which pertain to its operation in high-speed linear-word-selection memories. The device is used in the orthogonal mode, with an axial word field. The circumferential bit (digit) field coincides with the easy axis of magnetization, which is induced by a dc field during deposition of the film. The closed magnetic path avoids the limitation on thickness which exists in open-path elements. Thus, the cylindrical device can be designed to have large signals over a wide range of cycle times. Experimental data are included on the following characteristics: optimum device and drive-conductor geometry, effect on signals of one-zero duty cycle, sensitivity of stored information to disturbance by bit field and stray word fields, and drive-current requirements. The test specification developed from these data includes allowances for drive current tolerances, device temperature coefficient and information duty cycle. Sufficient quantities have been tested to this specification to show that this device is a workable, reproducible memory element. View full abstract»

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  • Tunnel Diode Delay-Line Memory

    Page(s): 269 - 272
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    This paper describes a memory system wherein bits of information are stored serially in time on electrical delay lines, The simplicity and speed of the basic storage cell makes large high-speed stores of this sort feasible. The paper stresses the basic principles of operation. A brief description of one such system model built to demonstrate these principles is included. View full abstract»

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  • Flux Divison in a Saturable Multipath Core

    Page(s): 272 - 277
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    An mmf drive NI is applied to the major leg of asaturable ferrite core whose three legs are initially at negative saturation. The resulting ¿¿ in the driven leg divides into the other two (minor) legs, one of which is loaded by a resistive load. This division of flux is analyzed, using for each leg the parabolic inelastic switching model ¿ = ¿peak (F) [1-(¿/¿sat)2], which is valid only if mf F is high enough to switch ¿ to positive saturation. Calculated plots of flux-division ratio D vs NI for various load values are in quite good agreement with experimental data, except in the region of low NI, where the parabolic mdel is invalid for the longer miner leg. View full abstract»

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  • Exploitation of Initial Conditions to Achieve Flux Gain and Nondestructive Readout in Balanced Magnetic Circuits

    Page(s): 278 - 284
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    A simple experiment on a magnetically-balanced circuit, consisting of a flux source and two equal-length parallel paths is outlined. It is observed that if a controlling signal causes one of the parallel paths to be preferred and this controlling signal is removed before switching is completed, the parallel path originally preferred continues to be preferred. The core equivalent of a balanced circuit is then examined to determine if this phenomenon is present there as well. It is found that the basic behavior of a balanced circuit and its core equivalent can be made the same, provided care is taken in setting up the same initial conditions in both circuits. It is shown that initial flux levels are important, as well as the rate at which these initial levels are established. An attempt is then made to relate, in a qualitative way, the circuit properties observed to known properties of a single core. It is observed that the properties which will be exploited here are present in most standard materials; however, a balanced circuit tends to exaggerate these properties. In Section II experiments on two balanced circuits interconnected with a 1:1 turns ratio coupling winding are described. This configuration has been found to have two stable states, the final state being dependent on the initial condition in one of the elements. Signal amplification has been achieved over at least a 4:1 range of drive currents. These results are readily explainable by reference to the element characteristics described in the first section. View full abstract»

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  • DC Accuracy in a Fast Boxcar Circuit Via a Comparator

    Page(s): 285 - 288
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    A capacitor-storage boxcar (i.e., zero-order hold) circuit is described, which has a one-half ¿sec sampling time and a 0-to 6-volt dynamic range, with less than 10-mv absolute error for a hold time of one second or less. No operational amplifier is used. In the new boxcar, feedback is applied via a difference amplifier comparator during sampling to make the readout voltage, not the voltage actually across the capacitor, equal to the input voltage. This effectively cancels any long-term voltage errors across either sampling switch or readout isolation amplifier. Eliminated are both offset voltage errors due to circuit assembly tolerances and also long-term offset drifts occurring over more than one storage interval, e.g., as due to temperature changes. The actual circuit given is all solid state, has no inductive or critical elements and has been easily reproduced several times. This comparator boxcar concept is not limited to capacitor storage. View full abstract»

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  • Transistorized Multiplier and Divider and Its Applications

    Page(s): 288 - 295
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    The inverse pair of logarithmic and exponential functions obtained from current voltage characteristics of junction transistors have been combined here to devise a direct method of analog multiplication and division which has an inherent tendency of self-compensation for the effects of temperature variation and also of mutual cancellation of nonlinear distortion arising in the individual stages. Experimental curves for both the operations show an accuracy of 2 per cent over a range of one and one-half decades in multiplication and about two decades in division. It has further been shown how this system may be used with comparative advantages to realize ac power and root law amplifiers, volume compressors and volume expandors of compandor systems, linear amplitude modulators and amplitude stabilizers. The experimental observations of ac nonlinear amplifiers designed to follow square and square root law response functions show that the respective characteristics hold good within an accuracy of 2 per cent over a range of 50 db. The use of these inverse relationships as a conventional 2 to 1 compressor followed by an expandor yields over-all compandor characteristics having a linearity over a range of 55 db with a maximum deviation of about 0.6 db from a straight line appearing only at the extreme end of the dynamic range. The analog multiplication has further been used to produce a linear amplitude modulation of about 95 per cent. View full abstract»

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  • Synthesis of Practical Three-Input Majority Logic Networks

    Page(s): 296 - 299
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    This paper deals with a method of realizing switching functions with three-input majority gates, utilizing a modification of the theory of Akers [1]. This approach attempts to minimize the total number of elements used for both gating and delay. The method derived is suitable for implementation on a digital computer and a program was written for the Burroughs 220 computer which produces excellent results for switching functions of 6 variables or less. Results of sample programs are given and limitations of the method are discussed. View full abstract»

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  • The Generation of Minimal Threshold Nets by an Integer Program

    Page(s): 299 - 302
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    This paper deals with the problem of generating a combinatorial network of threshold gates capable of evaluating a partially specified Boolean function. With the additional restriction that the network is to be cycle-free, the procedure described is designed to generate a network of minimum complexity in the sense that it is comprised of the smallest possible number of threshold elements. The essential result is a demonstration of the fact that the question of whether or not parameters exist such that a network of given complexity is capable of evaluating a given Boolean function is equivalent to the feasibility question for an associated integer program. In the case of feasibility the solution to the integer program contains the design of a minimum network realizing the given function. View full abstract»

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  • A Self-Organizing Drum

    Page(s): 302
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    First Page of the Article
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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope