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Electronic Computers, IEEE Transactions on

Issue 5 • Date Oct. 1963

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Displaying Results 1 - 25 of 53
  • [Front cover]

    Page(s): c1
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    Freely Available from IEEE
  • IEEE Professional Technical Group on Electronic Computers

    Page(s): nil1
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    Freely Available from IEEE
  • Breaker Page

    Page(s): nil1
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    Freely Available from IEEE
  • Realization of Logical Functions by a Network of Threshold Components with Specified Sensitivity

    Page(s): 443 - 454
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    In the realization of a logical function by a network of threshold components, one important engineering parameter is the tolerances which must be placed on the coefficients and threshold of the individual components. For threshold gates in which the logical ``zero'' corresponds to a constant signal of zero value and in which the coefficients are all positive or all negative, these tolerances are functions only of the gap boundaries of the map realized by the component. A set of theorems is presented that define ``algebraic-like'' operations which provide a means for performing a sequence of symbolic operations on the desired logical function whereby the latter is transformed into a description of a network of threshold components which is its realization. Using these theorems a procedure is given for realizing an arbitrary logical function as a network of threshold components with specified sensitivity. View full abstract»

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  • A Realization Procedure for Threshold Gate Networks

    Page(s): 454 - 461
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    One engineering parameter of importance in the realization of threshold gate networks is the tolerance which must be placed on the coefficients and threshold of the individual components. A previous paper gives a realization procedure which allows this tolerance to be controlled. The present paper gives an alternate realization procedure which also allows the tolerance to be controlled, but which is somewhat different in its application. The new procedure can be considered to be a generalization of an earlier procedure for the single-element realization problem. The function is first decomposed using a generalization of the function tree and then reconstructed using a generalization of the range theorem plus some additional simplification theorems. View full abstract»

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  • An Annotated Bibliography on NOR and NAND Logic

    Page(s): 462 - 464
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    A bibliography containing 63 references to papers dealing with NOR and NAND gate design and application composes this paper. References are primarily taken from journals published in the United States. They are mainly presented as an aid to those interested in this area of computer circuitry rather than as a listing of credit to those who have done work in NOR and NAND logic and related fields. A one or two sentence summary is given for each reference. View full abstract»

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  • General Synthesis of Tributary Switching Networks

    Page(s): 464 - 469
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    A synthesis procedure is described which generates all tributary networks (TRIBs) realizing a given truth function when no a priori assignment of the variables to input terminals is specified. If the truth function is not known to be realizable by a TRIB structure, the synthesis procedure provides a convenient test for TRIB realizability. If the variables are preassigned to input terminals, the synthesis and test are still applicable and correspondingly shorter. A major tool of the procedure is the matrix of binary representations of the minterms of the truth function¿the so called ``minterm matrix.'' The procedure is illustrated by a numerical example. View full abstract»

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  • kth-Order Finite Automaton

    Page(s): 470 - 475
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    A kth-order finite automaton is an automaton whose next state is a function of its most recent k states as well as its present input. A procedure to test whether a given ordinary automaton is equivalent to some kth-order automaton is suggested. View full abstract»

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  • The Effects of Interconnections on High-Speed Logic Circuits

    Page(s): 476 - 487
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    By way of worked examples in typical but somewhat idealized cases the effect on circuit speed of circuit interconnections is studied. The source, calculation and minimization of interconnection crosstalk is also discussed. It is shown that high-speed circuitry must be miniaturized and the implications are discussed. View full abstract»

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  • Optimization of Pulse and Digital Circuits by Use of the Lagrange Multiplier Technique

    Page(s): 488 - 492
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    Equations are derived for the optimal design of a frequency divider circuit, and optimal design equations are presented for other typical pulse circuits: a timing circuit, a gating circuit and a clipping circuit. The Lagrange Multiplier Technique used in this paper has also been applied successfully for the optimal design of switching amplifiers [1]. For each of the circuits considered, the reliability and the performance of the circuit are enhanced by adjusting circuit elements so as to maximize or minimize a specified variable of the circuit when the circuit is in one of its several states; when in other of its states, however, the circuit is required to perform in accordance with specified relationships which act as constraints on the optimization procedure. View full abstract»

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  • A Method of Theoretical Analysis of High-Speed Junction Diode Logic Circuits

    Page(s): 492 - 502
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    The charge storage (and, consequently, the recovery time) problem of a p-n junction diode has been a most troublesome phenomenon in the application of junction diodes in switching circuits. If many diodes in a logic gate are switched simultaneously from conduction to cutoff, large sums of stored charge will be generated and will tend to reverse the state of the nonswitching diodes in the same circuit. Accordingly, a possible false logic response may result. Unfortunately, the diode models presently available are useless for analyzing such transients. For this reason, a new diode model has been devised. From a study of the physical process in a junction diode, a unique relationship can be established between the terminal electric properties and the charge storage in the base material, of the diode. The relationship can be shown in a simple flowgraph. From this flowgraph a lumped charge model of a p-n junction diode is proposed. Utilizing this model, one can simply and uniquely solve the transient problems encountered in diode switching circuits, while only two parameters, the saturation current Is, and the diode time constant Td, are required to evaluate the solution numerically. View full abstract»

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  • A High-Speed Arithmetic Unit Using Tunnel Diodes

    Page(s): 503 - 511
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    This paper describes a high-speed arithmetic unit which utilizes a ``sub-multiple algorithm'' in both multiplication and division. The organization and circuits, which make the algorithm practical and economical, are presented. High performance in the unit is achieved by the use of tunnel diodes in four key areas, namely, in a tunnel diode memory using nondestructive readout, in the memory selection drivers, in a tunnel diode adder and in a bidirectional shift register. The unit performs a fixed point binary multiplication and division of two 44-bit operands in 2.75 ¿sec and 12 ¿sec, respectively. An experimental arithmetic unit has been built and operated in conjunction with a computer.1 Propagation delays of less than 2.2 nanoseconds were achieved between logic stages of a 48-bit binary full adder. Some results of the evaluation tests are also discussed. View full abstract»

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  • Variable Field-Length Data Manipulation in a Fixed Word-Length Memory

    Page(s): 512 - 516
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    Many medium-scale electronic computers currently are being designed to cater to scientific and business data-processing problems. Efficiency of floating point computation for scientific problems usually favors a fixed-word format and a word-oriented memory, so that a complete floating-point operand may be read out of or stored in memory in parallel. The logical processing of strings of characters not starting or ending on a word boundary, or the arithmetic processing of variable field-length fixed-point operands, are penalized. The penalty is the result of time-consuming combinations of masking and/or shifting which must be programmed before or after processing and before results can be stored. The purpose of this report is to describe several representative memory-access systems that avoid the housekeeping necessary for processing variable-length operands in a fixed word-length machine and to evaluate their relative efficiencies. View full abstract»

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  • A Dynamic Large Signal Model for a Single-Domain Thin Magnetic Film Inductor

    Page(s): 517 - 521
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    A dynamic large signal model for a thin film inductor consisting of two orthogonal windings wound around a thin single-domain film is developed. Based on Gilbert's modification of the Landau-Lifshitz equation describing the rotational behavior of the magnetization of the film, this model is valid for both large and small signals and for frequencies up to several hundred megacycles. As a result of the gyroscopic nature of mangetic behavior, the model of necessity contains as a part of its description a nonlinear second order differential equation in time. Until the external circuits connected to the inductor are specified, one cannot explicitly relate magnetic behavior and terminal voltages and currents. Instead one must seek a simultaneous solution of the differential equations describing the interconnected system. The utility of this model for analytically describing the behavior of thin film parametric devices such as parametrons, parametric amplifiers, balanced modulators, and flip-flops is mentioned but not discussed in detail. View full abstract»

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  • A New Method for Automatic Character Recognition

    Page(s): 521 - 526
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    This paper deals with the problem of reading numerical characters having strong variations in form, size and position. The method introduced here can describe the characters in invariant terms, with considerations of topological and morphological type. Therefore, it is called ``morphotopological method for character recognition'' and was applied to the construction of a very high performance reading machine. View full abstract»

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  • Linear and Nonlinear Interpolators

    Page(s): 526 - 532
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    When diode selection circuits are fed with signals that vary linearly with an input variable, they produce as output a convex or concave function consisting of one linear section per diode. In the present circuits, by combining each diode with a suitable series ``interpolating'' resistor, and feeding the output connection with constant current, it is possible to produce 2n-1 linear sections with n diodes. The use of voltage dependent interpolating resistors replaces the linear sections by nonlinear curves making possible the generation of smooth nonlinear functions. The function generator is stable as compared with similar nonlinear circuits because its transfer characteristic is independent of the nonlinearity of the resistors in a first approximation. Accuracies of the order 0.5 per cent of full scale output are readily obtainable even in the simplest circuit configurations. 1° phase shift occurs at frequencies of the order of 10 kc for nonlinear interpolation and up to several hundred kc for linear interpolation. The representative example of a squarer is described in detail; an error analysis is given and it is shown how the circuit can be compensated for a constant linear load. View full abstract»

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  • Deterministic and Stochastic Response of Linear Time Variable Systems

    Page(s): 532 - 540
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    The solution of the equations which describe a linear system and its variable parameters is usually difficult enough to warrant the use of a computer. This paper discusses and illustrates the use of analog computers in obtaining deterministic and stochastic responses of single or multiple input-output, time-variable systems. Stochastic response is emphasized with attention focused on the output or response, auto and cross-correlations. The response correlation matrix Rzz(t1,t2) which is evaluated from the adjoint system is also considered in terms of the general problem of random-initial values and random-forcing functions. View full abstract»

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  • A Fundamental Error Theory for Analog Computers

    Page(s): 541 - 550
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    The material presented here allows a fairly thorough analysis of deterministic errors in continuous systems. The methods outlined in other papers using sampled-data techniques permit the extension of this theory to include discrete systems such as DAA's and Digital Computers when used for solving differential equations using operational techniques. View full abstract»

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  • Correction

    Page(s): 550
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  • Bounds on Threshold Gate Realizability

    Page(s): 561 - 564
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    First Page of the Article
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Aims & Scope

This Transactions ceased publication in 1967. The current retitled publication is 

IEEE Transactions on Computers.

Full Aims & Scope