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IEE Proceedings E - Computers and Digital Techniques

Issue 4 • Jul 1992

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Displaying Results 1 - 10 of 10
  • Sequences and arrays derived from nonprimitive irreducible polynomials

    Publication Year: 1992, Page(s):363 - 371
    Cited by:  Papers (1)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (588 KB)

    The cycle set structure and correlation properties of the families of sequences generated by autonomous binary and multiple valued linear feedback shift registers are investigated. It is demonstrated that these sequence families arise on the rows and columns of pseudorandom arrays formed by folding certain m sequences over GF(q). Expressions are given for the weights and correlation values for cer... View full abstract»

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  • Corrected settling time of the distributed parallel arbiter

    Publication Year: 1992, Page(s):348 - 354
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (408 KB)

    In data buses used for interconnecting the constituent parts of a computer system, contention can arise if two or more of the modules attempt to acquire control of the bus at the same time. The distributed parallel arbiter is a widely-used means of resolving this contention; it consists of a combinational logic network distributed among all the modules. The time taken for the network to settle is ... View full abstract»

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  • Automated synthesis of digital multiplexer networks

    Publication Year: 1992, Page(s):329 - 334
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (344 KB)

    A programmed algorithm is presented for the synthesis and optimisation of networks implemented with multiplexer universal logic modules. The algorithm attempts level by level optimisation selecting the control variables that result in minimum number of continuing branches. Cascaded networks, if realisable, are always found and given preference over tree networks, though mixtures of cascade and tre... View full abstract»

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  • Time-range reasoning for microprocessor systems diagnosis: a probabilistic extension

    Publication Year: 1992, Page(s):308 - 310
    Cited by:  Papers (2)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (200 KB)

    The concept of time range has been recently proposed to capture the notion of time impreciseness in event occurrence, which is found to be of fundamental importance for temporal reasoning in the domain of microprocessor systems design and diagnosis. A possibility measure is implicitly implied in the time-range representation, although it is not properly quantified for effective temporal reasoning.... View full abstract»

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  • Remote password authentication with smart cards

    Publication Year: 1992
    Cited by:  Papers (5)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (64 KB)

    In a previous paper (ibid. vol.138, no.3, p.165-168, 1991) Chang and Wu proposed an efficient method for remote password authentication based on the Chinese remainder theorem (CRT). In this correspondence, the authors show that, in their scheme, anyone who possesses the public information in the network can derive some of the secret keys of the password generation centre. Then, that person can rev... View full abstract»

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  • Low-complexity synthesis of incompletely specified multiple-output mod-2 sums

    Publication Year: 1992, Page(s):355 - 362
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (524 KB)

    A new method for (quasi) minimisation of incompletely specified multiple-output mod-2 sum expressions is presented. It uses a new low-complexity algorithm for the Reed-Muller transform (RMT). Heuristically choosing a (quasi-)optimal polarity of the transform, its coefficients are combined so as to form a locally disjoint RM coefficient cover. Inverse RMT yields a (quasi)minimal exclusive-OR sum of... View full abstract»

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  • SAM-I: a prototype machine for dynamic, array-oriented programming languages

    Publication Year: 1992, Page(s):335 - 347
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1012 KB)

    Describes a distributed-function machine prototype for the indirect interpretation of array-oriented high-level language programs. The architecture was derived through simulation studies, seeded by Flynn and Hoevel's work with directly executable language techniques, and by Johnston's contour model. The SAM-I prototype demonstrates that the interpretation overhead of array-oriented high-level lang... View full abstract»

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  • Designing a complementary design rule checker based on a binary balanced quad list quad tree

    Publication Year: 1992, Page(s):311 - 322
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (688 KB)

    An efficient real time VLSI-CAD tool, the complementary design rule checker (CDRC), composed of one interactive phase and one batch phase is presented. It is a general geometrical design rule model which checks some of the layout constraints in the interactive phase and the other constraints in the batch phase. Those classified constraints are disjointed, and each one of them should be checked onl... View full abstract»

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  • Modelling and algorithms for spare allocation in reconfigurable VLSI

    Publication Year: 1992, Page(s):323 - 328
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (392 KB)

    One approach to enhancing the yield or reliability of large area VLSI structures has been by means of spare interconnect, logic and computational units. Although extensive literature exists concerning design for inclusion of spares and restructuring mechanisms in memories and processor arrays, little research has been published on general models and algorithms for broad classes of spare allocation... View full abstract»

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  • Switch-level fault detection and diagnosis environment for MOS digital circuits using spectral techniques

    Publication Year: 1992, Page(s):293 - 307
    Cited by:  Papers (8)
    IEEE is not the copyright holder of this material | Click to expandAbstract | PDF file iconPDF (1060 KB)

    A switch-level fault detection and diagnosis environment for MOS digital circuits using a compression data method based on a spectral signature is described. The selected fault model includes an MOS transistor permanently On and Off, breaks in internal gate lines, and shorts between two internal nodes of different logic gates, or between the internal nodes within the same complex gate. Circuit edi... View full abstract»

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