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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 12 • Date Dec. 2006

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Displaying Results 1 - 25 of 38
  • Table of contents

    Publication Year: 2006 , Page(s): C1 - C4
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  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2006 , Page(s): C2
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  • A Multigigahertz Multimodulus Frequency Divider in 90-nm CMOS

    Publication Year: 2006 , Page(s): 1333 - 1337
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (796 KB) |  | HTML iconHTML  

    This brief presents a multimodulus frequency divider with division ratio between 64 and 127 fabricated in 90-nm CMOS. By using a load-switching technique, high operating frequency, and low power static divider was achieved. The divider consists of six 2/3 divider stages. The maximum operating frequency is 4.7 GHz with current consumption 2.3 mA at low voltage supply 1.2 V and rms cycle-to-cycle jitter lower than 1 ps View full abstract»

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  • New Sliding-Mode Learning Law for Dynamic Neural Network Observer

    Publication Year: 2006 , Page(s): 1338 - 1342
    Cited by:  Papers (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (242 KB) |  | HTML iconHTML  

    This brief deals with a state observation problem when the dynamic model of a plant contains an uncertainty or it is completely unknown (only smoothness properties are assumed to be in force). The dynamic neural network approach is applied in this informative situation. A new learning law, containing relay (signum) terms, is suggested to be in use. The nominal parameters of this procedure are adjusted during the preliminary "training process" where the sliding-mode technique as well as the least-squares method are applied to obtain the "best" nominal parameter values using training experimental data. The upper bounds for the weights as well as for the averaged estimation error are derived. Two numeric examples illustrate this approach: first, the nonlinear third-order electrical system (Chua's circuit) with noises in the dynamics as well as in the output, and, second, the water ozone-purification process supplied by a bilinear model with unknown parameters View full abstract»

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  • Estimation of the Projection Operator in a Multiresolution Multisensor Data Fusion Scheme

    Publication Year: 2006 , Page(s): 1343 - 1347
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (181 KB) |  | HTML iconHTML  

    Zhang presented a new multiresolution multisensor data fusion scheme for dynamic systems to be observed by multisensors of different resolutions. State space projection equation is introduced to associate the states of a system at each resolution with others. A discrete model of the system is built by using Haar wavelet or general compactly supported wavelet as a linear projection operator to approximate the state space projection. In fact, different wavelet corresponds to different sensor structure. For the multiresolution multisensor system with unknown sensor structure, the projection operator should be estimated online. Up to now, this problem has never been investigated. In this brief, the projection operator is estimated by using least-square estimation algorithm and recursive least-square estimation algorithm. The research on projection operator estimation lays a foundation for the popularization and application of the multiresolution multisensor system estimation algorithm in the real system View full abstract»

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  • Capacitive Inter-Chip Data and Power Transfer for 3-D VLSI

    Publication Year: 2006 , Page(s): 1348 - 1352
    Cited by:  Papers (22)  |  Patents (8)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (737 KB) |  | HTML iconHTML  

    We report on inter-chip bidirectional communication and power transfer between two stacked chips. The experimental prototype system components were fabricated in a 0.5-mum silicon-on-sapphire CMOS technology. Bi-directional communication between the two chips is experimentally measured at 1Hz-15 MHz. The circuits on the floating top chip are powered with capacitively coupled energy using a charge pump. This is the first demonstration of simultaneous nongalvanic power and data transfer between chips in a stack. The potential use in 3-D VLSI is aimed at reducing costs and complexity that are associated with galvanic inter-chip vias in 3-D integration View full abstract»

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  • Joint Optimal Design of Digital Filters and State-Space Realizations

    Publication Year: 2006 , Page(s): 1353 - 1357
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (186 KB) |  | HTML iconHTML  

    In this brief, a procedure for digital filters design is presented. The main purpose is to show that a digital filter and its realization can be simultaneously determined such as to minimize an upper bound of the H2 norm of the estimation error and impose a certain degree of robustness against practical uncertainties as for instance, finite word length implementation, roundoff errors, and numerical precision. The optimal filter and its state-space realization are jointly determined from the solution of a convex programming problem expressed in terms of linear matrix inequalities. A simple illustrative example is presented for comparison purposes making clear the advantages of the reported results View full abstract»

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  • A 40-GHz Flip-Flop-Based Frequency Divider

    Publication Year: 2006 , Page(s): 1358 - 1362
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (814 KB) |  | HTML iconHTML  

    This brief presents the design and implementation of a 40-GHz flip-flop-based frequency divider which incorporates a novel latch topology with two distinct tail current sources and an enabled cross-coupled pair during the tracking mode. The proposed topology will speed up the latch operation and increase the driving capability. It is capable of performing frequency division at 40 GHz without shunt or series peaking inductors. The circuit was fabricated in a 0.18-mum SiGe BiCMOS process, where only CMOS transistors were used. It draws an average current of 5 mA from a 1.8-V supply voltage View full abstract»

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  • All-Digital Fast-Locked Synchronous Duty-Cycle Corrector

    Publication Year: 2006 , Page(s): 1363 - 1367
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (993 KB) |  | HTML iconHTML  

    An all-digital fast-locked synchronous duty-cycle corrector is presented. It corrects the duty cycle and synchronizes the input and output clocks in 10 clock cycles. The proposed circuit has been fabricated in a 0.18-mum CMOS technology. The measured duty-cycle error is between 1.5% and -1.4% for the input duty cycle of 40%~60%. The measured peak-to-peak jitter is 12.9ps at 1GHz. The measured operation frequency range is from 0.8GHz to 1.2 GHz View full abstract»

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  • An Efficient Scheme for Nonlinear Modeling and Predistortion in Mixed-Signal Systems

    Publication Year: 2006 , Page(s): 1368 - 1372
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (226 KB) |  | HTML iconHTML  

    A novel identification and predistortion scheme of weakly nonlinear systems for mixed-signal devices, which takes into account practical implementation aspects, is presented. It is well known that for the identification of weakly nonlinear systems, despite the spectral regrowth, it suffices to sample the input-output (I/O) data of the system at the Nyquist rate of the input signal. Many applications such as linearization and mixed-signal simulations require system models at a higher sampling rate than Nyquist. Up to now, the construction of such high-rate models has been done by oversampling the corresponding I/O data. This leads to high computational complexity, ill posedness of the estimation, and high demand on the analog-to-digital-converter sampling rate for the implementation. This brief discusses an efficient way to obtain high-rate models and predistorters from low-rate models and shows the validity of the proposed scheme for a very-high-speed-digital-subscriber-line power amplifier, where an adjacent channel power supression of 20 dB is achieved View full abstract»

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  • Switched-Current Filters Revisited: Square-Root Domain Sampled-Data Filters

    Publication Year: 2006 , Page(s): 1373 - 1377
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (260 KB) |  | HTML iconHTML  

    In this brief, the well-known switched-current (SI) filtering technique is revisited using the concept of the square-root domain (SRD) filtering. It is proved that SI filters are a subclass of the SRD filters, where sampled-data signal processing is performed. This is achieved by considering typical lossless and lossy SRD sampled-data integrator configurations, using a set of complementary SRD operators which are based on the quadratic I-V relationship of MOS transistor operated in the saturation. Circuit examples are given, where linear-domain integrator and third-order filter configurations were derived using appropriate SRD sampled-data building blocks View full abstract»

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  • Integrated Low-Loss CMOS Active Rectifier for Wirelessly Powered Devices

    Publication Year: 2006 , Page(s): 1378 - 1382
    Cited by:  Papers (80)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1426 KB)  

    A low-loss CMOS full-wave active rectifier is presented. It consists of two dynamically biased and symmetrically matched active diodes each realized by an nMOS switch driven by a 2-ns voltage comparator with reverse-current control. With a load of 1.8-kOmega, the rectified dc voltage is 3.22 V and 1.2 V for a 13.56 MHz ac sinusoidal input voltage of 3.5 V and 1.5 V respectively. It is fabricated in a 0.35-mum CMOS process with an active area of 0.0055 mm 2, with no low-threshold devices and on-chip passive components View full abstract»

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  • Quantizer Nonoverload Criteria in Sigma–Delta Modulators

    Publication Year: 2006 , Page(s): 1383 - 1387
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (311 KB) |  | HTML iconHTML  

    A simple method to guarantee absolute stability in multibit sigma-delta modulators (SDMs) is to ensure that the quantizer never overloads. This applies to any SDM. Derivation of the requirements for nonoverload have previously been shown for different types of modulators; the sigma-delta or output-feedback modulator with rounding quantizer as well as the error-feedback modulator using truncation. Here, these nonoverload requirements will be clarified and a unified formulation is presented that is not limited with regard to modulator topology or quantizer function View full abstract»

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  • Digital Frequency Synthesizer Based on Two Coprime Moduli DDS

    Publication Year: 2006 , Page(s): 1388 - 1392
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (419 KB) |  | HTML iconHTML  

    A new concept for direct digital synthesizer (DDS) design is presented in this brief. The originality of the method consists on the use of a traditional modulus 2L DDS and a novel modulus (2 L-1) DDS whose outputs are digitally mixed by means of a complex multiplier. This way, the number of different frequencies achievable equals 2L(2L-1) using two independent L-bits wide accumulators. No phase truncation is required resulting in extremely low spurs, while the size of the memories for the trigonometric look-up tables is only 2L positions. The design has been implemented in a field-programmable gate array to demonstrate its performance and logic requirements View full abstract»

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  • A Baud-Rate Timing Recovery Scheme With a Dual-Function Analog Filter

    Publication Year: 2006 , Page(s): 1393 - 1397
    Cited by:  Papers (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1173 KB) |  | HTML iconHTML  

    This brief presents a baud-rate timing recovery scheme that is aided by signals generated from a dual-function analog filter. The analog filter functions as a simultaneous low-pass and bandpass filter to generate the data and its slope, respectively. Peaking is introduced in the low-pass data path to equalize a lossy channel. The timing recovery loop utilizes the equalized data and slope signals obtained from the dual-function analog filter to recover a clock based on a modified minimum mean squared error (MMSE) criterion. Unlike previously published baud-rate techniques for multigigabit per second nonreturn-to-zero data, this technique can lock to either random or alternating data patterns, even from a closed eye. As a proof of concept, a prototype dual-function analog filter was fabricated in a 0.18-mum CMOS process and used to recover a 2-GHz clock from a 2-Gb/s 231-1 random data sequence based on the modified MMSE criterion View full abstract»

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  • An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch

    Publication Year: 2006 , Page(s): 1398 - 1402
    Cited by:  Papers (22)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (170 KB) |  | HTML iconHTML  

    This brief analyzes the effect of load capacitor mismatch on the offset of a regenerative latch comparator. Two analytical models are presented and compared with HSpice simulations. Our results indicate that in a typical 0.18-mum CMOS latch, a capacitive imbalance of only 1 fF can lead to offsets of several tens of millivolts View full abstract»

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  • Low-Complexity Symbol Detector for MIMO-OFDM-Based Wireless LANs

    Publication Year: 2006 , Page(s): 1403 - 1407
    Cited by:  Papers (10)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (571 KB) |  | HTML iconHTML  

    In this brief, a low-complexity hardware architecture for multiple-input multiple-output (MIMO) orthogonal frequency-division multiplexing (OFDM) symbol detectors with two transmit and two receive antennas is proposed. The detectors support two MIMO-OFDM schemes of space-frequency block coded OFDM and space-division multiplexing OFDM in order to achieve higher performance and throughput. However, symbol detection processes for these two schemes have high computational complexity, which is a burden to hardware implementation of MIMO-OFDM symbol detectors. In order to reduce complexity, the proposed symbol detector is designed with shared architecture, where similar functional blocks are merged and share the hardware resources, and results in the reduction of logic gates by 34% over a conventional architecture employing two individual detectors View full abstract»

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  • Analysis of the Bridged T-Coil Circuit Using the Extra-Element Theorem

    Publication Year: 2006 , Page(s): 1408 - 1412
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (165 KB) |  | HTML iconHTML  

    The bridged T-coil (BTC) circuit is often employed to extend the bandwidth of a wideband amplifier beyond the transition frequency fT of the driver device. Although the optimal design solution is well known, extreme algebraic complexity has caused its derivation to remain arcane. This brief presents an analysis of the BTC circuit using the extra element theorem which breaks the overall problem down into a series of simple network analyses and produces the final result as the product of the transfer function without the "extra element" and a multiplicative correction factor. The design is completed by using pole-zero cancellation to reduce the order of the transfer functions View full abstract»

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  • On the Dynamics of Regenerative Frequency Dividers

    Publication Year: 2006 , Page(s): 1413 - 1417
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (725 KB) |  | HTML iconHTML  

    A comprehensive analytical study of regenerative frequency dividers (RFD) is presented. The study includes two fundamental modes of operation in RFDs, namely locked (or stable) and quasi-locked modes, and the study also covers the transition from free-running oscillation to quasi-locked, and ultimately to locked operation mode. Differential equations characterizing the RFD behavior for both operation modes as well as the transition between the two are derived. An RFD circuit for Bluetooth applications was designed and fabricated in a 65-nm CMOS process with a supply voltage of 1.2 V. Measurement results of the RFD prototype verify the accuracy of the proposed analytical models View full abstract»

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  • Gyrator Realization Based on a Capacitive Switched Cell

    Publication Year: 2006 , Page(s): 1418 - 1422
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (251 KB) |  | HTML iconHTML  

    Efficient power gyrator realization by means of a controlled switch cell is presented. It is shown that a switching cell may be controlled so as to acquire low-frequency gyrative characteristics (on average). A realization suitable for operation with current sources is presented, that employs a switched capacitor. Due to the capacitive input, a gyrator of this nature is suitable for operation with current sources. The main applications of such gyrators are expected in superconductive magnetic energy storage systems and current-fed converters, due to the stiff-current characteristic imposed by a magnetic storage element. Other possible applications include sources with softer i-v characteristics, such as photovoltaic generators and sources of significant output inductance View full abstract»

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  • Modified Form of Liu-Michel's Criterion for Global Asymptotic Stability of Fixed-Point State-Space Digital Filters Using Saturation Arithmetic

    Publication Year: 2006 , Page(s): 1423 - 1425
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (89 KB) |  | HTML iconHTML  

    A criterion for the global asymptotic stability of fixed-point state-space digital filters using saturation arithmetic was previously given by Liu and Michel. A modified form of their criterion is presented View full abstract»

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  • A 3.125-Gbit/s Parallel Optical Receiver in 0.13-μm CMOS With Direct Crosstalk Power Penalty Measurement Capability

    Publication Year: 2006 , Page(s): 1426 - 1430
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (2134 KB) |  | HTML iconHTML  

    We introduce a new method to measure the crosstalk power penalty in an arrayed environment by using an on-chip pseudorandom-bit-sequence generator to drive the aggressors. The proposed method is implemented in a three-channel 3.125-Gbit/s/ ch parallel receiver. Experimental results are presented including measurements of bit-error rate and crosstalk power penalty for 2.5and 3.125-Gbit/s operations. The measured crosstalk power penalty is less than 1 dB at both data rates. The test chip was designed in a standard 0.13-mum CMOS process View full abstract»

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  • A Low-Voltage Fast Switching Frequency Synthesizer for FH-SS Applications

    Publication Year: 2006 , Page(s): 1431 - 1435
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (269 KB) |  | HTML iconHTML  

    This brief presents a novel 2.7-V frequency synthesizer for frequency hopping spread spectrum applications. To accomplish fast switching, the frequency synthesizer utilizes a memory access technique to retrieve the precalibrated and digitized tuning voltage values. The phase noise and the frequency accuracy of the frequency synthesizer are analyzed. The channel efficiency, the frequency switching performance, and the output spectral purity are investigated at 2.4 GHz. Measurement shows that the channel switching time is 5 mus. Thus, the proposed synthesizer is promising for frequency hopping wireless communication. The developed architecture is ready to be used for application-specified integrated circuit design View full abstract»

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  • A Low-Power CMOS Linear-in-Decibel Variable Gain Amplifier With Programmable Bandwidth and Stable Group Delay

    Publication Year: 2006 , Page(s): 1436 - 1440
    Cited by:  Papers (19)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (804 KB) |  | HTML iconHTML  

    This brief presents a new circuit architecture for linear-in-decibel, constant-bandwidth variable gain amplifier (VGA). To obtain high linearity under low-voltage operation, this VGA is a closed-loop structure. In loop amplifier design, two techniques are applied: first, the loop amplifier is given finite input impedance. This arrangement keeps the VGA bandwidth constant under different gain setting. Second, a current-buffered compensation is applied for loop stability. Compared to the Miller compensation, this method achieves wider bandwidth. The prototype chip using 0.18-mum CMOS technology demonstrates that -10- to 20-dB gain and 0.5- to 30-MHz bandwidth can be programmed independently. The group delay difference within 30-dB gain control range is smaller than 1%. The total circuit dissipates 1.35 mA from a 1.8-V supply View full abstract»

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  • Magnetic-Feedback-Based Predistortion Method for Low-Noise Amplifier Linearization

    Publication Year: 2006 , Page(s): 1441 - 1445
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (285 KB) |  | HTML iconHTML  

    A predistortion method for CMOS low-noise amplifiers (LNAs) to be used in broadband wireless applications is presented. The method is based on the nulling of the third-order intermodulation distortion of the main amplifier by a highly nonlinear predistortion branch. Maximum nonlinearity product cancellation is ensured by a transformer feedback method. The technique improves linearity in a wide range of input power without significant gain and noise figure (NF) degradation. Simulation results on a 1-V LNA indicate a 10.3-dB improvement in the third-order input intercept point with a degradation of only 1 and 0.44 dB in amplifier gain and NF, respectively. The design is based on a 0.13-mum CMOS technology View full abstract»

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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope