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Circuits, Devices and Systems, IEE Proceedings -

Issue 6 • Date Dec. 2006

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Displaying Results 1 - 11 of 11
  • Cascaded noise figure calculations for radio receiver circuits with noise-aliasing properties

    Publication Year: 2006 , Page(s): 517 - 524
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (456 KB)  

    A new modified form of the Friis equation for the noise figure of a cascade of stages that can be used when one or more of the stages in the cascade have noise-aliasing properties is derived. The application of the modified noise figure equation in the noise analysis of a subsampling receiver front-end is given and the equation is verified in a circuit-level simulation. The modified Friis equation... View full abstract»

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  • Equivalent circuit model of a stacked inductor for high-Q on-chip RF applications

    Publication Year: 2006 , Page(s): 525 - 532
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1226 KB)  

    A novel design for a stacked inductor using RLC elements is presented. The proposed model used to predict the stacked inductor is based on a 4-port circuit design with semi-empirical derivation. The modified RS formulas are implemented accurately to predict the series resistance of the stacked inductor. The verification has been carried out using a mature 0.18 mum process to fabricate s... View full abstract»

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  • Efficient and flexible architecture for AES

    Publication Year: 2006 , Page(s): 533 - 538
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (129 KB)  

    A new flexible AES architecture is proposed that can perform both encryption and decryption with 128-, 192-, and 256-bit key options by a novel on-the-fly key generation module. The corresponding subkeys for encryption and decryption are generated concurrently as the appropriate configuration parameters (signals) are set. The proposed design operates in CBCk (cipher block chain) mode and processes... View full abstract»

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  • CORDIC-based unified VLSI architecture for implementing window functions for real time spectral analysis

    Publication Year: 2006 , Page(s): 539 - 544
    Cited by:  Papers (1)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (475 KB)  

    Frequency analysis using DFT (discrete Fourier transform) or its faster computational technique (FFT) is an obvious choice for the entire image and signal processing domain where spectral leakage or picket fence effect is a major problem. Earlier works describe the software and ROM-based implementation of windowing functions to overcome the above-mentioned problems during spectral analysis. In thi... View full abstract»

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  • Packing-based VLSI module placement using genetic algorithm with sequence-pair representation

    Publication Year: 2006 , Page(s): 545 - 551
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (178 KB)  

    The sequence-pair, a data structure with applications in packing-based VLSI module placement, has received significant amounts of research effort as the core of simulated annealing optimisers. Nevertheless, its application within genetic algorithm frameworks has not been adequately investigated. This paper presents a genetic algorithm approach to rectangle packing using the sequence-pair. The meth... View full abstract»

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  • Fully differential current-mode third-order Butterworth VHF Gm-C filter in 0.18 μlm CMOS

    Publication Year: 2006 , Page(s): 552 - 558
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (1727 KB)  

    The authors present a new fully differential current-mode third-order Butterworth very high frequency Gm-C filter using current-mode linear transformation (CMLT) techniques. The systematic design method and procedure are developed to realise CMLT Gm-C filters efficiently. A third-order Butterworth lowpass filter with 200 MHz cutoff frequency, embedded bandgap reference and bi... View full abstract»

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  • Statistical modelling and design guidelines of CMOS current references

    Publication Year: 2006 , Page(s): 559 - 564
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (151 KB)  

    Two CMOS current reference circuits are analysed from a statistical point of view. The analysis provides two analytical models, one for each circuit, which allow designers to understand and predict the statistical behaviour of the output current as a function of the statistical behaviour of circuit components. Theoretical models are validated by means of both simulation and measurement results and... View full abstract»

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  • Noise-tolerance improvement in dynamic CMOS logic circuits

    Publication Year: 2006 , Page(s): 565 - 573
    Cited by:  Papers (3)
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (913 KB)  

    Dynamic CMOS logic styles are widely used in high-performance systems due mainly to their speed. However they have lower noise-tolerance than their static CMOS counterparts. To overcome this disadvantage a new noise-tolerant circuit technique, suitable for precharge-evaluate dynamic circuits, is presented. The technique is suitable for TSPC and domino gates. Comparisons with previously reported no... View full abstract»

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  • High-speed self-timed carry-skip adder

    Publication Year: 2006 , Page(s): 574 - 582
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (301 KB)  

    An efficient self-timed carry-skip adder with low area overhead and fast operation is proposed. The adder combines delay-insensitive and bounded delay completion signal detection techniques to define a novel, reliable, area-efficient and high-speed completion-detection circuit. The circuit employs double-rail encoded carry signals together with process-tracking delay circuit elements to efficientl... View full abstract»

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  • Approximation of arbitrary complex filter responses and their realisation in log domain

    Publication Year: 2006 , Page(s): 583 - 590
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (702 KB)  

    Approximation and design methods of a general class of IIR complex functions without any required symmetrical property are examined. A set of routines has been developed to allow arbitrary amplitude approximation of such asymmetrical functions. Approximation routines will include such features as high-order touch points in both passband and stopband regions, fixed poles and zeros and arbitrary fre... View full abstract»

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  • Hybrid multi-polarity arithmetic-Walsh transform

    Publication Year: 2006 , Page(s): 591 - 598
    Save to Project icon | Click to expandAbstract | PDF file iconPDF (213 KB)  

    A novel combined multi-polarity arithmetic-Walsh transform is introduced in which recursive relationships between higher and lower matrix orders of hybrid multi-polarity arithmetic-Walsh transform are developed. The new multi-polarity transform has a structure similar to that of the multi-polarity Walsh and multi-polarity arithmetic transform matrices, so it combines the computational advantages o... View full abstract»

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