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IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Issue 11 • Date Nov. 2006

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Displaying Results 1 - 18 of 18
  • Table of contents

    Publication Year: 2006, Page(s): C1
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems publication information

    Publication Year: 2006, Page(s): C2
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  • An Integrated Approach to Thermal Management in High-Level Synthesis

    Publication Year: 2006, Page(s):1165 - 1174
    Cited by:  Papers (12)  |  Patents (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (789 KB) | HTML iconHTML

    Thermal effects are becoming an important factor in the design of integrated circuits due to the adverse impact of temperature on performance, reliability, leakage, and chip packaging costs. Making all phases of the design flow aware of this physical phenomenon helps in reaching faster design closure. In this paper, we present an integrated approach to thermal management in architectural synthesis... View full abstract»

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  • A Scalable Synthesis Methodology for Application-Specific Processors

    Publication Year: 2006, Page(s):1175 - 1188
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1166 KB) | HTML iconHTML

    Custom processors based on application-specific or domain-specific instruction sets are gaining popularity, and are often used to implement critical architectural blocks in complex systems-on-chip. While several advances have been made in the area of custom processor architectures, tools, and design methodologies, designers are still required to manually perform some critical tasks, such as select... View full abstract»

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  • Integrating Physical Constraints in HW-SW Partitioning for Architectures With Partial Dynamic Reconfiguration

    Publication Year: 2006, Page(s):1189 - 1202
    Cited by:  Papers (40)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (723 KB) | HTML iconHTML

    Partial dynamic reconfiguration is a key feature of modern reconfigurable architectures such as the Xilinx Virtex series of devices. However, this capability imposes strict placement constraints such that even exact system-level partitioning (and scheduling) formulations are not guaranteed to be physically realizable due to placement infeasibility. We first present an exact approach for hardware-s... View full abstract»

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  • Instruction-Based Self-Testing of Delay Faults in Pipelined Processors

    Publication Year: 2006, Page(s):1203 - 1215
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (686 KB) | HTML iconHTML

    Aggressive processor design methodology using high-speed clock and deep submicrometer technology is necessitating the use of at-speed delay fault testing. Although nearly all modern processors use pipelined architecture, no method has been proposed in literature to model these for the purpose of test generation. This paper proposes a graph theoretic model of pipelined processors and develops a sys... View full abstract»

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  • A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI)

    Publication Year: 2006, Page(s):1216 - 1226
    Cited by:  Papers (13)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1059 KB) | HTML iconHTML

    This paper presents a new technique for detecting delay faults by observing the fault effects within slack intervals. Delay faults are detected through a comparison of the circuit outputs captured in the scan flip-flops with those from a matched known good neighboring die on the wafer. These outputs are captured in the flip-flops at multiple capture intervals, each progressively shorter than the n... View full abstract»

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  • Improving Linear Test Data Compression

    Publication Year: 2006, Page(s):1227 - 1237
    Cited by:  Papers (19)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (471 KB) | HTML iconHTML

    The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The ideas proposed in this paper transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing compression while still keeping all the test cubes in the output space. Scan inversion is used to invert a subset of the scan cells wh... View full abstract»

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  • Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories

    Publication Year: 2006, Page(s):1238 - 1249
    Cited by:  Papers (18)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1406 KB) | HTML iconHTML

    The techniques known in literature for the design of SRAM structures with low standby leakage typically exploit an additional operation mode, named the sleep mode or the standby mode. In this paper, existing low leakage SRAM structures are analyzed by several SPEC2000 benchmarks. As expected, the examined SRAM architectures have static power consumption lower than the conventional 6-T SRAM cell. H... View full abstract»

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  • Sleepy Stack Leakage Reduction

    Publication Year: 2006, Page(s):1250 - 1263
    Cited by:  Papers (33)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1770 KB) | HTML iconHTML

    Leakage power consumption of current CMOS technology is already a great challenge. International Technology Roadmap for Semiconductors projects that leakage power consumption may come to dominate total chip power consumption as the technology feature size shrinks. Leakage is a serious problem particularly for CMOS circuits in nanoscale technology. We propose a novel ultra-low leakage CMOS circuit ... View full abstract»

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  • Clustering for Processing Rate Optimization

    Publication Year: 2006, Page(s):1264 - 1275
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (548 KB) | HTML iconHTML

    Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level may have timing closure problems at post-layout stages due to the emergence of multiple-clock-period interconnects. Consequently, a tradeoff between clock frequency and throughput may be needed to meet the design requiremen... View full abstract»

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  • Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization

    Publication Year: 2006, Page(s):1276 - 1281
    Cited by:  Papers (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (439 KB) | HTML iconHTML

    Logic gates as repeaters (LGRs)-a methodology for delay optimization of CMOS logic circuits with resistance-capacitance (RC) interconnects is described. The traditional interconnect segmentation by insertion of repeaters is generalized to segmentation by distributing logic gates over interconnect lines, reducing the number of additional, logically useless inverters. Expressions for optimal segment... View full abstract»

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  • Analysis and Implementation of Multiple–Input, Multiple–Output VBLAST Receiver From Area and Power Efficiency Perspective

    Publication Year: 2006, Page(s):1281 - 1286
    Cited by:  Papers (2)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (510 KB) | HTML iconHTML

    This paper presents an analysis of the vertical Bell Laboratories layered space time (VBLAST) receiver used in a multiple-input multiple-output (MIMO) wireless system from the hardware implementation perspective and identifies those processing elements that consume more area and power due to complex signal processing. This paper models a scalable VBLAST receiver based on minimum mean square error ... View full abstract»

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  • Architectures for Dynamic Data Scaling in 2/4/8K Pipeline FFT Cores

    Publication Year: 2006, Page(s):1286 - 1290
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (610 KB) | HTML iconHTML

    This paper presents architectures for supporting dynamic data scaling in pipeline fast Fourier transforms (FFTs), suitable when implementing large size FFTs in applications such as digital video broadcasting and digital holographic imaging. In a pipeline FFT, data is continuously streaming and must, hence, be scaled without stalling the dataflow. We propose a hybrid floating-point scheme with tail... View full abstract»

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  • 2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

    Publication Year: 2006, Page(s): 1291
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  • Search for Editor-In-Chief of IEEE Transactions on Very Large Scale Integration (VLSI) Systems

    Publication Year: 2006, Page(s): 1292
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems society information

    Publication Year: 2006, Page(s): C3
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  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems Information for authors

    Publication Year: 2006, Page(s): C4
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Aims & Scope

Design and realization of microelectronic systems using VLSI/ULSI technologies requires close collaboration among scientists and engineers in the fields of systems architecture, logic and circuit design, chips and wafer fabrication, packaging, testing, and systems applications. Generation of specifications, design, and verification must be performed at all abstraction levels, including the system, register-transfer, logic, circuit, transistor, and process levels. To address this critical area through a common forum, the IEEE Transactions on VLSI Systems was founded.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

Krishnendu Chakrabarty
Department of Electrical Engineering
Duke University
Durham, NC 27708 USA
Krish@duke.edu