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Electron Devices, IEEE Transactions on

Issue 12 • Date Dec. 2006

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Displaying Results 1 - 25 of 46
  • Table of contents

    Page(s): C1 - 2858
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  • IEEE Transactions on Electron Devices publication information

    Page(s): C2
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  • Changes to the Editorial Board

    Page(s): 2859
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  • Kudos to Our Reviewers

    Page(s): 2860
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  • The Golden List

    Page(s): 2861 - 2877
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  • Confidentiality of the Review Process

    Page(s): 2878
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  • Quaternary InGaAsSb Thermophotovoltaic Diodes

    Page(s): 2879 - 2891
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    InxGa1-xAsySb1-y thermophotovoltaic (TPV) diodes were grown lattice matched to GaSb substrates by metal-organic vapor phase epitaxy in the bandgap range of EG = 0.5 to 0.6 eV. InGaAsSb TPV diodes, utilizing front-surface spectral control filters, are measured with thermal-to-electric conversion efficiency and power density (PD) of nTPV = 19.7% and PD = 0.58 W/cm2, respectively, for a radiator temperature of Tradiator = 950 degC, diode temperature of Tdiode = 27 degC, and diode bandgap of EG = 0.53 eV. Practical limits to TPV energy conversion efficiency are established using measured recombination coefficients and optical properties of front surface spectral control filters which for 0.53-eV InGaAsSb TPV energy conversion are nTPV = 28% and PD = 0.85 W/cm2 at the above operating temperatures. The most severe performance limits are imposed by 1) diode open-circuit voltage (VOC) limits due to intrinsic Auger recombination and 2) parasitic photon absorption in the inactive regions of the module. Experimentally, the diode VOC is 15% below the practical limit imposed by intrinsic Auger recombination processes. Analysis of InGaAsSb diode electrical performance versus diode architecture indicates that VOC and thus efficiency are limited by extrinsic recombination processes such as through bulk defects View full abstract»

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  • Investigation of Self-Heating Effects in Submicrometer GaN/AlGaN HEMTs Using an Electrothermal Monte Carlo Method

    Page(s): 2892 - 2900
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    An electrothermal Monte Carlo (MC) method is applied in this paper to investigate electron transport in submicrometer wurtzite GaN/AlGaN high-electron mobility transistors (HEMTs) grown on various substrate materials including SiC, Si, GaN, and sapphire. The simulation method is an iterative technique that alternately runs an MC electronic simulation and solves the heat diffusion equation using an analytical thermal resistance matrix method. Results demonstrate how the extent of the thermal droop in the Id-Vds characteristics and the device peak temperature depend upon both the biasing conditions and the substrate material type. Polarization effects are considered in the simulations, as they greatly influence electron transport in GaN/AlGaN HEMTs by creating a highly concentrated two-dimensional electron gas (2DEG) at the GaN/AlGaN interface. It is shown that a higher 2DEG density provides the devices with a better current handling capability but also increases the importance of the thermal effects View full abstract»

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  • Further Suppression of Surface-Recombination of an InGaP/GaAs HBT by Conformal Passivation

    Page(s): 2901 - 2907
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    Conformal passivation on an InGaP/GaAs HBT with significant reduction in the base surface-recombination effect is demonstrated. Not only dc behaviors but also RF performances are remarkably improved compared with the conventional emitter-ledge structure. Based on the conformal passivation, i.e., the base surface is covered by the depleted InGaP ledge structure and sulfur ((NH4)2Sx ) treatment, lower base surface-recombination current density, lower specific contact resistance, lower sheet resistance, higher current gain, higher collector current, and higher maximum oscillation frequency are obtained View full abstract»

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  • High-Temperature Operation of AlGaN/GaN HFET With a Low on-State Resistance, High Breakdown Voltage, and Fast Switching

    Page(s): 2908 - 2913
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    Improved characteristics of an AlGaN/GaN HFET are reported. In this paper, the authors introduce a new ohmic electrode of Ti/AlSi/Mo and a low refractive index SiNx to decrease the contact resistance and gate leakage current. The AlGaN/GaN HFET showed a low specific resistance of 6.3 mOmega middot cm2 and a high breakdown voltage of 750 V. The switching characteristics of an AlGaN/GaN HFET are investigated. The small turn-on delay of 7.2 ns, which was one-tenth of Si MOSFETs, was measured. The switching operation of the HFET showed no significant degradation up to 225 degC View full abstract»

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  • At-Bias Extraction of Access Parasitic Resistances in AlGaN/GaN HEMTs: Impact on Device Linearity and Channel Electron Velocity

    Page(s): 2914 - 2919
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    AlGaN/GaN high-electron mobility transistor "hot" parasitic source and drain resistances RS,D are determined under operating biases through wideband S-parameter measurements, without the use of "ColdFET" biasing conditions. Both RS and RD are found to increase dramatically over ColdFET values, both for biases approaching threshold and for open-channel conditions. Parasitic resistance values have a significant effect on the extracted small-signal equivalent circuit model elements, as well as on the apparent device linearity. The bias dependence of access resistances modifies the understanding of the transistor physical operation: A revised delay time analysis accounting for the bias dependence of parasitic resistances shows that the effective average electron velocity in the AlGaN/GaN two-dimensional electron-gas channel is approximately equal to 1.9 times 107 cm/s. This new value of channel velocity is also consistent with the CGS/gMO ratio obtained when the bias dependence of RS and RD is accounted for during the extraction of the transistor small-signal equivalent circuit model View full abstract»

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  • 50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

    Page(s): 2920 - 2925
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    Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system View full abstract»

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  • The Effect of an Fe-doped GaN Buffer on off-State Breakdown Characteristics in AlGaN/GaN HEMTs on Si Substrate

    Page(s): 2926 - 2931
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    An Fe-doped GaN buffer layer was employed in the growth of AlGaN/GaN high-electron mobility transistors (HEMTs) on Si substrates. In order to investigate the effects of an Fe-doped GaN buffer on OFF-state breakdown characteristics, HEMT devices with an Fe-doped GaN buffer on Si substrates were fabricated along with conventional devices utilizing an unintentionally doped GaN buffer on Si substrates. The device characteristics were compared. While HEMT devices with the conventional structure showed an extremely unstable OFF-state breakdown behavior due to punchthrough to the Si substrate, it was demonstrated that an Fe-doped GaN buffer layer on a Si substrate successfully suppressed the premature failure caused by Si-induced breakdown. As a result, the AlGaN/GaN HEMTs with an Fe-doped GaN buffer on Si substrates exhibited much more consistent and enhanced breakdown voltages, when compared with the conventional devices. Consequently, it is highly desirable that AlGaN/GaN HEMTs on Si substrates have an Fe-doped GaN buffer layer in order to achieve stable and robust OFF-state breakdown characteristics View full abstract»

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  • Current Collapse and High-Electric-Field Reliability of Unpassivated GaN/AlGaN/GaN HEMTs

    Page(s): 2932 - 2941
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    Long-term ON-state and OFF-state high-electric-field stress results are presented for unpassivated GaN/AlGaN/GaN high-electron-mobility transistors on SiC substrates. Because of the thin GaN cap layer, devices show minimal current-collapse effects prior to high-electric-field stress, despite the fact that they are not passivated. This comes at the price of a relatively high gate-leakage current. Under the assumption that donor-like electron traps are present within the GaN cap, two-dimensional numerical device simulations provide an explanation for the influence of the GaN cap layer on current collapse and for the correlation between the latter and the gate-leakage current. Both ON-state and OFF-state stresses produce simultaneous current-collapse increase and gate-leakage-current decrease, which can be interpreted to be the result of gate-drain surface degradation and reduced gate electron injection. This study shows that although the thin GaN cap layer is effective in suppressing surface-related dispersion effects in virgin devices, it does not, per se, protect the device from high-electric-field degradation, and it should, to this aim, be adopted in conjunction with other technological solutions like surface passivation, prepassivation surface treatments, and/or field-plate gate View full abstract»

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  • A Physical Model for On-Chip Spiral Inductors With Accurate Substrate Modeling

    Page(s): 2942 - 2949
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    A physical-based analytical model for on-chip inductors is developed. A ladder structure is used to model the skin and proximity effects in metal lines. The substrate electric and substrate magnetic losses are accurately modeled by RC and RL ladder structures, respectively. The effective inductance reduction due to the eddy current in the lossy silicon substrate at high frequency is modeled by a negative mutual inductance between the inductor and the substrate. All the model parameters can be calculated from the layout and process parameters. On-chip inductors with different geometries and substrate resistivities were fabricated for the verifications. The measured results are in very good agreement with the proposed model. This generic model can be applied to various substrate resistivities; thus, it is suitable for different technologies. This model can facilitate the design and optimization of on-chip inductors for RF IC applications View full abstract»

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  • Modeling of Gate Current and Capacitance in Nanoscale-MOS Structures

    Page(s): 2950 - 2957
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    By applying a fully self-consistent solution of the Schrodinger-Poisson equations, a simple unified approach has been developed in order to study the gate current and gate capacitance of nanoscale-MOS structures with ultrathin dielectric layer. In this paper, the model has been employed to investigate various gate structure and material combinations, thereby demonstrating wide applicability of the present model in the design of nanoscale-MOSFET devices. The results obtained by applying the proposed model are in good agreement with experimental data and previous models in the literature. A new result concerning optimum nitrogen content in HfSiON high-k gate-dielectric structure reported in this paper requires experimental verification through device fabrication View full abstract»

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  • Field-Emission Breakdown and Electromigration in Insulated Planar Nanoscopic Contacts

    Page(s): 2958 - 2964
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    Planar nanoscopic contacts are observed to undergo early electrical breakdown. The authors show that the cause is high field emission capable of triggering electromigration. The phenomenon is well described by an empirical current-voltage law, well different from that usually found in nonflat field emitters; this is attributed to the particular geometry of the contacts. Although the mathematical form of the law is always the same, the intensity of breakdown current changes from sample to sample, ranging over several orders of magnitude; this is explained by the nanoscopic roughness of the emitting surfaces. They also show that the occurrence of breakdown may be dependent on the polarity of the applied voltage View full abstract»

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  • A Quantum-Corrected Monte Carlo Study on Quasi-Ballistic Transport in Nanoscale MOSFETs

    Page(s): 2965 - 2971
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    In this paper, the authors study a quasi-ballistic transport in nanoscale Si-MOSFETs based upon a quantum-corrected Monte Carlo device simulation to explore an ultimate device performance. It was found that, when a channel length becomes shorter than 30 nm, an average electron velocity at the source-end of the channel increases due to ballistic transport effects, and then, it approaches a ballistic limit in a sub-10-nm regime. Furthermore, the authors elucidated a physical mechanism creating an asymmetric momentum distribution function at the source-end of the channel and the influences of backscattering from the channel region. The authors also demonstrated that an electron injection velocity at a perfectly ballistic transport is independent of the channel length and corresponds well to a prediction from Natori's analytical model View full abstract»

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  • The Hole Role in Solid-State Imagers

    Page(s): 2972 - 2980
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    The importance of holes present in the pixels of solid-state image sensors is described by Theuwissen et al. (IEDM Tech. Dig. 2005, p. 817). Today's success of digital imaging is based on the positive effect of an accumulation layer that reduces the interface-related dark current and dark current fixed-pattern noise. This superb imaging feature is applied in charge-coupled devices as well as in complementary metal-oxide-semiconductor devices, in consumer as well as in professional equipment. Holes are not only used to improve the dark performance of imagers; other examples of efficient use of holes are fixing electrostatic potentials, creating gate structures, draining photon-generated charges, and constructing antiblooming means View full abstract»

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  • High-Temperature Degradation of GaN LEDs Related to Passivation

    Page(s): 2981 - 2987
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    This paper describes the thermally activated failure mechanisms of GaN light-emitting diode (LED)-test structures related with the presence of a hydrogen-rich SiN passivation layer. It is shown that the properties of the passivation layer can remarkably affect devices' stability during high-temperature stress: Degradation mechanisms identified consist of radiative efficiency loss, emission crowding, and forward-current decrease. The radiative efficiency degradation was found to be thermally activated, with activation energy equal to 1.3 eV. This failure mechanism of LEDs is attributed to the thermally activated indiffusion of hydrogen from the passivation layer to p-type region of the diodes, with subsequent p-doping compensation and/or worsening of the transport properties of the p-side ohmic contact and p-type semiconductor View full abstract»

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  • A High Dynamic Range CMOS Image Sensor With Inpixel Light-to-Frequency Conversion

    Page(s): 2988 - 2992
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    A high dynamic range CMOS image sensor with inpixel light-to-frequency conversion has been designed. The prototype chip was fabricated in a standard 0.18-mum single-poly six-metal CMOS technology. The experimental results show that, operating at 1.2 V, the sensor can achieve a linear dynamic range of over 115 dB and an overall dynamic range of over 130 dB View full abstract»

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  • Negative Bias Temperature Instability in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

    Page(s): 2993 - 3000
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    The authors have proved that negative bias temperature instability (NBTI) is an important reliability issue in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The measurements revealed that the threshold-voltage shift is highly correlated to the generation of grain-boundary trap states. Both these two physical quantities follow almost the same power law dependence on the stress time; that is, the same exponential dependence on the stress voltage and the reciprocal of the ambient temperature. In addition, the threshold-voltage shift is closely associated with the subthreshold-swing degradation, which originates from dangling bond formation. By expanding the model proposed for bulk-Si MOSFETs, a new model to explain the NBTI-degradation mechanism for LTPS TFTs is introduced View full abstract»

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  • Fast Vth Instability in HfO2 Gate Dielectric MOSFETs and Its Impact on Digital Circuits

    Page(s): 3001 - 3011
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    Fast component of Vth instability in MOSFET with HfO 2 gate dielectric is systematically measured and characterized. A charge-trapping/detrapping model is used to simulate the Vth instability with overall agreement with the experiments. Experimental and modeling data provide and predict the fast Vth shift under both static and dynamic stress conditions. These data are incorporated into HSpice circuit simulation to evaluate the impact of Vth shift on the performance of digital circuit in realistic situations. Considering the properties of the fast Vth instability, circuit performance can be optimized by circuit design in addition to process improvements. This should be included to the guideline of process development and circuit design for future CMOSFET digital systems View full abstract»

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  • Edge Profile Effect of Tunnel Oxide on Erase Threshold-Voltage Distributions in Flash Memory Cells

    Page(s): 3012 - 3019
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    The erase threshold-voltage (VT) distribution in Flash electrically erasable programmable read-only memory cells was investigated versus the tunnel oxide edge profiles in self-aligned shallow trench isolation (SA-STI) and self-aligned poly (SAP) cells. The capacitive coupling with offset voltage correction is transcribed into VT transient for simulating erase VT dispersion without numerous full structure device simulations. It is shown that SAP gives rise to smaller VT dispersion, compared with SA-STI. The VT dispersion resulting from variations in dielectric thickness and oxide edge profiles is shown to fall far short of observed VT distribution, calling for examination of additional process and cell parameters View full abstract»

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  • Embedded Source/Drain SiGe Stressor Devices on SOI: Integrations, Performance, and Analyses

    Page(s): 3020 - 3024
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    A detailed investigation of embedded source/drain SiGe stressors (eSiGes) on a silicon-on-insulator substrate for pMOS performance enhancement is presented. It is found that the integration with undoped SiGe epitaxy suffers strain relaxation from a postepitaxy implantation. SiGe growth with in situ doping is able to retain high strain for carrier mobility enhancement. For doped eSiGe integration with a proper thermal sequence, 20% pMOS drive current improvement is demonstrated. Quantitative analyses of contributions from mobility enhancement and device exterior resistance reduction to the performance improvement are also discussed View full abstract»

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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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Meet Our Editors

Acting Editor-in-Chief

Dr. Paul K.-L. Yu

Dept. ECE
University of California San Diego