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Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Issue 6 • Date Jun 1992

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Displaying Results 1 - 13 of 13
  • An algorithm for exact rectilinear Steiner trees for switchbox with obstacles

    Page(s): 446 - 455
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (872 KB)  

    The switchbox rectilinear Steiner tree problem is to construct an optimal rectilinear Steiner tree interconnecting n terminals on the perimeter of a switchbox without crossing any obstacles inside the switchbox. However, intersecting boundaries of obstacles are allowed. An algorithm that computes an optimal switchbox rectilinear Steiner tree in O(F1(k)n+F2 (k)) time, where k is the number of obstacles inside the switchbox and F1 and F2 are exponential functions of k, is presented. For any constant k, the proposed algorithm runs in O(n) time. As an immediate extension, m Steiner trees are generated in O(mn) time, and the best one among them is selected View full abstract»

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  • Minimal factorization of rational matrix functions

    Page(s): 440 - 445
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (416 KB)  

    The theorem on minimal factorization of rational matrix functions without a pole or zero at infinity is extended to arbitrary rational matrix functions. To obtain this generalization, the concept of a centered realization for possibly nonproper rational matrix function is developed. A centered realization involves a single state-space operator and has most properties of a usual state-space realization View full abstract»

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  • Finite gain compensated double-sampled switched-capacitor integrators for high-Q bandpass filters

    Page(s): 425 - 431
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    A technique for the compensation of the operational amplifier (op-amp) finite gain error in the switched-capacitor (SC) integrator is proposed. Two possible SC integrators implementing the proposed technique are given. Both implementations allow the use of the double-sampling technique to increase by a factor of two the maximum speed of operation. The compensation operation consists in memorizing a sequence of output values of the SC integrator, and using them in the proper clock period to compensate the error due to the nonideal virtual ground. The compensation is mostly effective in a narrow frequency range centered around one specific frequency. The circuits implementing this technique are therefore particularly useful for high-Q high-frequency bandpass filters. The case of a biquadratic bandpass filter is reported as an example View full abstract»

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  • Full-wave precision rectification that is performed in current domain and very suitable for CMOS implementation

    Page(s): 456 - 462
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (488 KB)  

    An approach for implementation of full-wave precision rectifiers in CMOS technology is presented, in which the rectification is performed in current domain while both input and output signals are voltages. The rectifier has a very simple structure and both noninverting and inverting circuits can be realized with one op-amp, two current mirrors, and six MOS transistors. The performances of the proposed rectifiers are analyzed and discussed. Extensive computer simulation and experimental results obtained with this and other types of precision rectifiers, which demonstrate many advantages of the proposed techniques over others, are presented View full abstract»

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  • A condition for global convergence of a class of symmetric neural circuits

    Page(s): 480 - 483
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    A sufficient condition is proved guaranteeing that a class of neural circuits that includes the Hopfield model as a special case is globally convergent towards a unique stable equilibrium. The condition only requires symmetry and negative semi-definiteness of the neuron connection matrix T and is extremely simple to check and apply in practice. The consequences of the above result are discussed in the context of neural circuits for optimization of quadratic cost functions View full abstract»

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  • The extreme eigenvalues and stability of Hermitian interval matrices

    Page(s): 463 - 466
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    The author presents a Kharitonov-like algorithm to find the minimal and maximal eigenvalues, i.e. the root clustering interval, of a set of (n×n)-dimensional Hermitian interval matrices. It is proven that the maximal eigenvalue of a given set of Hermitian interval matrices coincides with the maximal eigenvalue of a special set of Hermitian vertex matrices while its minimal eigenvalue coincides with the minimal eigenvalue of another such special set of the same size. As immediate corollaries of this algorithm, necessary and sufficient conditions for testing Hurwitz and Schur stability of Hermitian interval matrices wherein one has to test stability of certain Hermitian vertex matrices are obtained View full abstract»

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  • A bound for the zeros of polynomials

    Page(s): 476 - 478
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    A new kind of circular bound on the zeros of polynomials is derived by determining Cauchy's bound on zeros of its transformed pair first. The transformation is based on a nonlinear transformation of the variable, which conceptually should give a better upper bound. The advantage of such a transformation is illustrated through several examples that show the improvement over the existing bounds. Convergence of the bound after iterative transformations of the original polynomial is also examined View full abstract»

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  • On robust Schur property of discrete-time polynomials

    Page(s): 467 - 470
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    Markov-like parameters have been defined for a discrete-time polynomial recently and a new method of Schur stability analysis of such polynomials has been established in the space of such parameters. These results are generalized for the Schur invariance property, and the maximum allowable variation in the associated parameters is obtained via evaluating some corner points. The result presented gives a quick qualitative measure of stability robustness of discrete-time polynomials View full abstract»

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  • A reconfigurable op-amp/DDA CMOS amplifier architecture

    Page(s): 484 - 487
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    A simple architecture for a configurable op-amp or differential difference amplifier (DDA) is presented. The circuitry can be configured as an input/output rail to rail high-speed op-amp, or as a DDA. The circuit was simulated using SPICE and fabricated in a 2-μm CMOS process through MOSIS. Configured as an op-amp, it achieves a positive and negative slew rate of 16 V/μs, a unity gain frequency of 14 MHz, and an open loop differential gain of 68 dB with a power consumption of 6 mW at 5-V supply. The circuit was also tested and found to work satisfactorily as a differential difference amplifier for frequencies up to about 10 MHz with a differential input range limited to 200 mV View full abstract»

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  • Application of robust control to sustained oscillations in power systems

    Page(s): 470 - 476
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    Transient control of the sustained oscillations that can occur after a major disturbance to a power system is investigated. A control scheme for an n-generator system is first developed using a classical machine model, and then extended to a machine model that includes governor/turbine dynamics. The proposed control strategies are linear and require only local relative angle and velocity measurements for the classical model case, plus the measurement of mechanical power if governor/turbine dynamics are included. Using Lyapunov's direct method, the control is shown to be robust with respect to parameter and load variations, and topology changes in the power system. The overall power system is shown to be exponentially stable in the main so that any oscillation, anywhere in the system, can be damped efficiently. The results are obtained without any linearization of the power system model. Simulation results for the 30-bus New England system demonstrate the effectiveness of the proposed control View full abstract»

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  • Stability and dynamics of delay-type general and cellular neural networks

    Page(s): 487 - 490
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    Several stability results and additional properties of the delay-type neural network and cellular network dynamics are proved. As a typical example, it is proved that if the feedback and delayed feedback matrices are nonnegative and their sum is irreducible, then the neural network is stable View full abstract»

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  • Varistor control of inductive transients

    Page(s): 478 - 480
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    It is shown that the varistor, a nonlinear resistor with current-voltage characteristics of the form i=ken , can be used to achieve superior limitation of inductive transients over that obtainable with a simple diode, or with a diode plus additional linear resistance. To this end a transient analysis is made of the circuit composed of the inductor, its internal linear resistance, and a shunt varistor when the source circuit is opened. The resultant differential equation, though nonlinear, is integrable in terms of elementary functions, and general results are presented in mathematical and graphical form for the current and voltage transients. For all n>1, the transient is found to reach zero in a finite time rather than asymptotically. For a given voltage rise when the source circuit is opened (a basic design parameter), the Zener diode yields the shortest transient. Except for the lowest values of n, the varistor is shown to approach the performance of the Zener diode, while offering practical advantages View full abstract»

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  • An efficient multilevel placement technique using hierarchical partitioning

    Page(s): 432 - 439
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    Ratio cut hierarchical partitioning, which enables efficient multilevel simulated annealing, is applied to the row placement problem for large circuits. An overlapping moving window scheme is used to compensate for the effect of partitioning on the placement quality. Through the use of hierarchical partitioning, the asymptotic run time complexity of this algorithm grows linearly as the function of the circuit size. The system is called placement by ratio cut partitioning (PRC). The results from several benchmark tests are presented demonstrating PRC to be 2.49% on average better than TimberWolfSC Ver5.6. Furthermore, the run time for PRC is 18.3% on average less than that required for TimberWolfSC Ver5.6 for large test cases with more than 2000 cells. For a 100-K sea of gates test case, a 7.09% reduction in total wire length over TimberWolfSC Ver5.6 and a 51.7% saving in CPU time were achieved View full abstract»

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