By Topic

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Issue 12 • Date Dec. 2006

Filter Results

Displaying Results 1 - 25 of 47
  • Table of contents

    Publication Year: 2006 , Page(s): C1 - C4
    Save to Project icon | Request Permissions | PDF file iconPDF (43 KB)  
    Freely Available from IEEE
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems publication information

    Publication Year: 2006 , Page(s): C2
    Save to Project icon | Request Permissions | PDF file iconPDF (39 KB)  
    Freely Available from IEEE
  • Variability-Aware Multilevel Integrated Spiral Inductor Synthesis

    Publication Year: 2006 , Page(s): 2613 - 2625
    Cited by:  Papers (29)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (788 KB) |  | HTML iconHTML  

    To successfully design spiral inductors in increasingly complex and integrated mixed-signal systems, effective design automation techniques must be created. In this paper, the authors develop an automated synthesis methodology for integrated spiral inductors to efficiently generate Pareto-optimal designs based on application requirements. At its core, the synthesis approach employs a scalable multilevel single-objective optimization engine that integrates the flexibility of deterministic pattern search optimization with the rapid convergence of local nonlinear convex optimization. Multiobjective optimization techniques and surrogate functions are utilized to approximate Pareto surfaces in the design space to locate Pareto-optimal spiral inductor designs. Using the synthesis methodology, the authors also demonstrate how to reduce the impact of process variation and other sources of modeling error on spiral inductors. The results indicate that the multilevel single-objective optimization engine locates near-optimal spiral inductor geometries with significantly fewer function evaluations than current techniques, whereas the overall synthesis methodology efficiently optimizes inductor designs with an improvement of up to 51% in key design constraints while reducing the impact of process variation and modeling error View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Reducing Conflict Misses by Application-Specific Reconfigurable Indexing

    Publication Year: 2006 , Page(s): 2626 - 2637
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1061 KB)  

    The predictability of memory access patterns in embedded systems can be successfully exploited to devise effective application-specific cache optimizations. In this paper, an improved indexing scheme for direct-mapped caches, which drastically reduces the number of conflict misses by using application-specific information, is proposed. The indexing scheme is based on the selection of a subset of the address bits. With respect to similar approaches, the solution has two main strengths. First, owing to an analytical model for the conflict-miss conditions of a given trace, it provides a symbolic algorithm to compute the optimum solution (i.e., the subset of address bits to be used as cache index that minimize the number of conflict misses). Second, owing to a reconfigurable bit selector that can be programmed at run time, it allows the optimal cache indexing to fit to a given application. Results show an average reduction of conflict misses of 24%, measured over a set of standard benchmarks, and for different cache configurations View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Circuit Reliability Analysis Using Symbolic Techniques

    Publication Year: 2006 , Page(s): 2638 - 2649
    Cited by:  Papers (32)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (374 KB) |  | HTML iconHTML  

    Due to the shrinking of feature size and the significant reduction in noise margins, nanoscale circuits have become more susceptible to manufacturing defects, noise-related transient faults, and interference from radiation. Traditionally, soft errors have been a much greater concern in memories than in logic circuits. However, as technology continues to scale, logic circuits are becoming more susceptible to soft errors than memories. To estimate the susceptibility to errors in combinational logic, the use of binary decision diagrams (BDDs) and algebraic decision diagrams (ADDs) for the unified symbolic analysis of circuit reliability is proposed. A framework that uses BDDs and ADDs and enables the analysis of combinational circuit reliability from different aspects, e.g., output susceptibility to error, influence of individual gates on individual outputs and overall circuit reliability, and the dependence of circuit reliability on glitch duration, amplitude, and input patterns, is presented. This is demonstrated by the set of experimental results, which show that the mean output error susceptibility can vary from less then 0.1% for large circuits and short glitches (20% cycle time) to about 30% for very small circuits and long enough glitches (50% cycle time) View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Design Exploration With Imprecise Latency and Register Constraints

    Publication Year: 2006 , Page(s): 2650 - 2662
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (950 KB) |  | HTML iconHTML  

    This paper proposes a design exploration framework that considers impreciseness in design specification. In high-level synthesis, imprecise information is often encountered. Two types of impreciseness are considered, namely: 1) impreciseness underlying on functional unit specifications and 2) impreciseness due to system constraints, i.e., latency and register constraints. The framework is iterative and based on a core scheduling called "register-constrained inclusion scheduling." An example of how the scheduling algorithm works is shown. The effectiveness of the proposed framework for imprecise specification is demonstrated by exploring a design solution for three well-known benchmarks, namely: 1) discrete cosine transform; 2) Voltera filter; and 3) fast Fourier transform. The selected solution meets the acceptability criteria while minimizing the total number of registers View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Latency-Guided On-Chip Bus-Network Design

    Publication Year: 2006 , Page(s): 2663 - 2673
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (883 KB)  

    Deep submicrometer technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in critical paths being dominated by global interconnect rather than gate delays. Second, an ultrahigh level of integration mandates design of systems-on-chip that encompass numerous design blocks of decreased functional granularity and increased communication demands. The convergence of these two factors emphasizes the importance of the on-chip bus network as one of the crucial high-performance enablers for future systems-on-chip. An on-chip bus-network design methodology and corresponding set of tools which, for the first time, close the synthesis loop between system and physical design have been developed. The approach has three components: a communication profiler, a bus-network designer, and a fast approximate floorplanner. The communication profiler collects run-time information about the traffic between system cores. The bus-network design component optimizes the bus-network structure by coordinating information from the other two components. The floorplanner aims at creating a feasible floorplan; it also sends feedback about the most constrained parts of the network. The effectiveness of our bus-network design approach on a number of multicore designs is demonstrated View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Retiming and Resynthesis: A Complexity Perspective

    Publication Year: 2006 , Page(s): 2674 - 2686
    Cited by:  Papers (11)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (273 KB) |  | HTML iconHTML  

    Transformations using retiming and resynthesis operations are the most important and practical (if not the only) techniques used in optimizing synchronous hardware systems. Although these transformations have been studied extensively for over a decade, questions about their optimization capability and verification complexity are not answered fully. Resolving these questions may be crucial in developing more effective synthesis and verification algorithms. This paper settles the above two open problems. The optimization potential is resolved through a constructive algorithm which determines if two given finite state machines (FSMs) are transformable to each other via retiming and resynthesis operations. Verifying the equivalence of two FSMs under such transformations, when the history of iterative transformation is unknown, is proved to be polynomial-space-complete and hence just as hard as general equivalence checking, contrary to a common belief. As a result, we advocate a conservative design methodology for the optimization of synchronous hardware systems to ameliorate verifiability. Our analysis reveals some properties about initializing FSMs transformed under retiming and resynthesis. On the positive side, a lag-independent bound is established on the length increase of initialization sequences for FSMs under retiming. It allows a simpler incremental construction of initialization sequences compared to prior approaches. On the negative side, we show that there is no analogous transformation-independent bound when resynthesis and retiming are iterated. Nonetheless, an algorithm computing the exact length increase is presented View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Protecting Combinational Logic Synthesis Solutions

    Publication Year: 2006 , Page(s): 2687 - 2696
    Cited by:  Papers (9)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (457 KB)  

    Recently, design reuse has emerged as a dominant design and system-integration paradigm for modern systems on silicon. However, the intellectual-property-business model is vulnerable to many dangerous obstructions, such as misappropriation and copyright fraud. The authors propose a new method for intellectual-property protection that relies upon design watermarking at the combinational-logic-synthesis level. They introduce two protocols for embedding user- and tool-specific information into a logic network while performing multilevel logic minimization and technology mapping, two standard-optimization processes during logic synthesis. The hidden information can be used to protect both the design and the synthesis tool. The authors demonstrate that the difficulty of erasing or finding a valid signature in the synthesized design can be made arbitrarily computationally difficult. In order to evaluate the developed-watermarking method, the authors applied it to a standard set of real-life benchmarks, where high probability of authorship was achieved with negligible overhead on solution quality View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Joint Power Management of Memory and Disk Under Performance Constraints

    Publication Year: 2006 , Page(s): 2697 - 2711
    Cited by:  Papers (7)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (553 KB) |  | HTML iconHTML  

    This paper presents a method to combine memory resizing and disk shutdown to achieve better energy savings than can be achieved individually. The method periodically adjusts the size of physical memory and the timeout value to shut down a hard disk to reduce the average energy consumption. Pareto distributions are used to model the disk idle time. The parameters of the distributions are estimated at runtime and used to calculate the appropriate timeout value. The memory size is changed based on the predicted number of disk accesses at different memory sizes. The method also considers the delay caused by power management and limits the performance degradation. The method is simulated and compared with other power management methods. Simulation results show that the method consistently achieves better energy savings and less performance degradation across different workloads View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Cycle-Based Decomposition of Markov Chains With Applications to Low-Power Synthesis and Sequence Compaction for Finite State Machines

    Publication Year: 2006 , Page(s): 2712 - 2725
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (389 KB) |  | HTML iconHTML  

    This paper advances the state of the art by presenting a well-founded mathematical framework for modeling and manipulating Markov processes. The key idea is based on the fact that a Markov process can be decomposed into a collection of directed cycles with positive weights, which are proportional to the probability of the cycle traversals in a random walk. Two applications of this new formalism in the computer-aided design area are studied. In the first application, the authors present a new state assignment technique to reduce dynamic power consumption in finite state machines. The technique comprises of first decomposing the state machine into a set of cycles and then performing a state assignment by using Gray codes. The proposed encoding algorithm reduces power consumption by an average of 15%. The second application is sequence compaction for improving the efficiency of dynamic power simulators. The proposed method is based on the cycle decomposition of the Markov process representing the given input sequence and then selecting a subset of these cycles to construct the compacted sequence View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Efficient Low-Power Repeater-Insertion Scheme

    Publication Year: 2006 , Page(s): 2726 - 2736
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (508 KB) |  | HTML iconHTML  

    Previous repeater-insertion algorithms for power minimization of realistic interconnect trees under given timing budgets are often time consuming. In this paper, the problem of runtime reduction for low-power repeater insertion is investigated. Specifically, a power-sensitivity analysis that links the algorithm runtime and the power dissipation result to the selection of repeater library and candidate repeater locations is performed. Based on the analysis, possible repeater locations and potential repeater widths are selected to increase the efficiency of the low-power repeater-insertion algorithm, achieving a judicious tradeoff between runtime and power savings. Moreover, a novel repeater-insertion algorithm based on the Lagrangian relaxation framework is proposed. The proposed algorithm combines a local optimizer based on the dynamic programming (DP) technique and a fast global search engine using the "ellipsoid method." As a result, the proposed approach is capable of producing high-quality solutions at a very fast speed and without manual tuning of the algorithm parameters. A repeater-insertion tool called Freeze, which uses the proposed algorithm, is developed and applied to various interconnect trees with different timing targets. Experimental results demonstrate the high effectiveness of the proposed approach. In comparison with the state-of-the-art low-power repeater-insertion schemes, Freeze requires 5.8 times fewer iterations on the average, achieving a speedup of up to 9.1 times with even better power savings. When compared with a DP-based scheme, which guarantees the optimal solution, the proposed tool delivers a speedup of up to 14.6 times with less than 2% power increase on the average View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Energy-Optimal Speed Control of a Generic Device

    Publication Year: 2006 , Page(s): 2737 - 2746
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (380 KB) |  | HTML iconHTML  

    The dynamic voltage and frequency scaling technique in CPUs is an example of adjusting a device's control variable to trade off power consumption and performance. This idea of energy optimization through speed control has been subsequently applied to other components of electronic systems such as disk drives and wireless transceivers. In this paper, the energy-optimal speed profile (a function of time) of a generic device that has to execute a given task in a given time is obtained analytically. The proposed approach is applicable to devices with either discrete or continuous-speed sets. The main novelty of the approach is that for discrete-speed sets, the nature of the underlying continuous power-speed relationship does not need to be known. The discrete power-speed data points only need to satisfy a W-convex relation: a discrete analog of a convex function. Based on the observation that most devices have W-convex power-speed relations, it is shown that the optimal speed profile uses at most one speed (for continuous speeds) or two speeds (for discrete-speed sets). Furthermore, each device has an intrinsic speed (independent of the task) uc at which it consumes the least energy per unit work done. It is shown that this speed can be calculated directly from measured values of power-speed data points (for discrete-speed sets) or by an experimental line search procedure where each step involves measuring a power-speed data point (for continuous-speed sets). In either case, no curve fit or knowledge of analytical power models is required. The optimum speed profile was shown to be either uc or the minimum feasible speed(s) for the given task, with the choice depending on the energy overheads and task parameters View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Wafer Topography-Aware Optical Proximity Correction

    Publication Year: 2006 , Page(s): 2747 - 2756
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (526 KB)  

    Depth of focus is the major contributor to lithographic process margin. One of the major causes of focus variation is imperfect planarization of fabrication layers. Presently, optical proximity correction (OPC) methods are oblivious to the predictable nature of focus variation arising from wafer topography. As a result, designers suffer from manufacturing yield loss as well as loss of design quality through unnecessary guardbanding. In this paper, the authors propose a novel flow and method to drive OPC with a topography map of the layout that is generated by chemical-mechanical polishing simulation. The wafer topography variations result in local defocus, which the authors explicitly model in the OPC insertion and verification flows. In addition, a novel topography-aware optical rule check to validate the quality of result of OPC for a given topography is presented. The experimental validation in this paper uses simulation-based experiments with 90-nm foundry libraries and industry-strength OPC and scattering bar recipes. It is found that the proposed topography-aware OPC (TOPC) can yield up to 67% reduction in edge placement errors. TOPC achieves up to 72% reduction in worst case printability with little increase in data volume and OPC runtime. The electrical impact of the proposed TOPC method is investigated. The results show that TOPC can significantly reduce timing uncertainty in addition to process variation View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Timeless Discretization of Magnetization Slope in the Modeling of Ferromagnetic Hysteresis

    Publication Year: 2006 , Page(s): 2757 - 2764
    Cited by:  Papers (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (265 KB) |  | HTML iconHTML  

    A new methodology is presented to assure numerically reliable integration of the magnetization slope in the Jiles-Atherton model of ferromagnetic core hysteresis. Two hardware description language (HDL) implementations of the technique are presented: one in SystemC and the other in very-high-speed integrated circuit (VHSIC) HDL (VHDL) analog and mixed signal (AMS). The new model uses timeless discretization of the magnetization slope equation and provides superior accuracy and numerical stability especially at the discontinuity points that occur in hysteresis. Numerical integration of the magnetization slope is carried out by the model itself rather than by the underlying analog solver. The robustness of the model is demonstrated by practical simulations of examples involving both major and minor hysteresis loops View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping

    Publication Year: 2006 , Page(s): 2765 - 2774
    Cited by:  Papers (29)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (348 KB) |  | HTML iconHTML  

    An analytical model is proposed to compute the fringe capacitance between two nonoverlapping interconnects in different layers using a conformal mapping technique. With this technique, electric field lines are geometrically approximated to separately model the different capacitive components. These components are finally combined to obtain the equivalent fringe capacitance. Using the aforementioned technique, a model was developed to compute the capacitances of typical interconnect geometries using technology-dependent parameters. The proposed model closely matches with FASTCAP results and significantly reduces the computational complexity and time in calculating the interconnect capacitances View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Resampling Plans for Sample Point Selection in Multipoint Model-Order Reduction

    Publication Year: 2006 , Page(s): 2775 - 2783
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (425 KB) |  | HTML iconHTML  

    Multipoint projection methods have gained much notoriety in model-order reduction of linear, nonlinear, and parameter-varying systems. A well-known difficulty with such methods lies in the need for clever point selection to attain model compactness and accuracy. In this paper, the authors present a method for sample point selection in multipoint projection-based model-order reduction. The proposed technique, which is borrowed from the statistical modeling area, is based on resampling schemes to estimate error and can be coupled with recently proposed order reduction schemes to efficiently produce accurate models. Two alternative implementations are presented: 1) a rigorous linear-matrix-inequality-based technique and 2) a simpler, more efficient, heuristic search. The goal of this paper is to answer two questions. First, can this alternative metric be effective in selecting sample points in the sense of placing points in regions of high error without recourse to evaluation of the larger system? Second, if the metric is effective in this sense, under what conditions are substantial improvements in the model reduction efficiency achieved? Results are shown that indicate that the metric is indeed effective in a variety of settings, therefore opening the possibility for performing adaptive error control View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Length-Matching Routing Algorithm for High-Performance Printed Circuit Boards

    Publication Year: 2006 , Page(s): 2784 - 2794
    Cited by:  Papers (18)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (630 KB) |  | HTML iconHTML  

    As the clock frequencies used in industrial applications increase, the timing requirements imposed on routing problems become tighter. Therefore, it becomes important to route the nets within tight minimum and maximum length bounds. Although the problem of routing nets to satisfy maximum length constraints is a well-studied problem, there exists no sophisticated algorithm in literature that ensures that minimum length constraints are also satisfied. In this paper, the authors propose a novel algorithm that effectively incorporates the min;max length constraints into the routing problem. The approach is to use a Lagrangian-relaxation (LR) framework to allocate extra routing resources around nets simultaneously during routing them. The authors also propose a graph model that ensures that all the allocated routing resources can be used effectively for extending lengths. Their routing algorithm automatically prioritizes resource allocation for shorter nets and length minimization for longer nets so that all nets can satisfy their min;max length constraints. This paper demonstrates that this algorithm is effective even in the cases where length constraints are tight, and the spacing between adjacent nets is small View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Floorplan Design for Multimillion Gate FPGAs

    Publication Year: 2006 , Page(s): 2795 - 2805
    Cited by:  Papers (12)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (603 KB) |  | HTML iconHTML  

    Modern field-programmable gate arrays (FPGAs) have multimillions of gates and future generations of FPGAs will be even more complex. This means that floorplanning tools will soon be extremely important for the physical design of FPGAs. Due to the heterogeneous logic and routing resources of an FPGA, FPGA floorplanning is very different from the traditional floorplanning for application-specific integrated circuits. This paper presents the first FPGA-floorplanning algorithm targeted for FPGAs with heterogeneous resources (e.g., Xilinx's Spartan3 chips consisting of columns of configurable logic blocks, RAM blocks, and multiplier blocks). This algorithm can generate floorplans for Xilinx's XC3S5000 architecture (largest of the Spartan3 family) in a few minutes View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking

    Publication Year: 2006 , Page(s): 2806 - 2819
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (470 KB) |  | HTML iconHTML  

    In this paper, the authors introduce the concept of zero-change netlist transformations (ZCNTs) to: 1) quantify the suboptimality of existing placers on artificially constructed instances and 2) "partially" quantify the suboptimality of placers on synthesized netlists from arbitrary netlists by giving lower bounds to the suboptimality gap. Given a netlist and its placement from a placer, a class of netlist transformations that synthesizes a different netlist from the given netlist is formally defined, but yet the new netlist has the same half-perimeter wire length (HPWL) on the given placement. Furthermore, and more importantly, the optimal HPWL value of the new netlist is no less than that of the original netlist. By applying the transformations and reexecuting the placer, any deviation in HPWL as a lower bound to the gap from the optimal HPWL value of the new synthesized netlist can be interpreted. The transformations allow us to: 1) increase the cardinality of hyperedges; 2) reduce the number of hyperedges; and 3) increase the number of two-pin edges, while maintaining the placement HPWL constant. It is developed here methods that apply ZCNTs to synthesize netlists having typical netlist statistics. Furthermore, an approach to estimate the suboptimality of other metrics, such as rectilinear minimum-spanning tree (RMST) and minimum-Steiner tree, is extended. Using these transformations, the suboptimality of some of the existing academic placers (FengShui, Capo, mPL, Dragon) is studied on synthesized netlists from the IBM benchmarks with instances ranging from 10k to 210k placeable instances. The results show that current placers exhibit suboptimal behavior to ZCNTs with varying degree according to the placer. Systematic suboptimality deviations in HPWL and RMST are displayed on the synthesized netlists from IBM (version 1) benchmarks. The specific nature of the transformations points out troublesome netlist structures and possible directions for improvement in the- existing placers View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States

    Publication Year: 2006 , Page(s): 2820 - 2832
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (592 KB) |  | HTML iconHTML  

    Static power consumption due to subthreshold, gate, and junction leakages has become a significant component of the total power consumption. For nanoscale circuits, leakage poses one of the most important challenges to the continuation of Moore's law. The leakage of a logic gate varies by an order of magnitude over its Boolean input space. Thus, one way to minimize leakage in a circuit during standby mode is to apply an input vector for which the leakage is at its minimum. Such a set of vectors is called the minimum leakage set (MLS). In this paper, an efficient algorithm for computing the exact MLS is presented. The approach is based on implicit enumeration using integer-valued decision diagrams. Since the search space for MLS is exponential in the number of primary inputs, the enumeration is done with respect to the minimum balanced cut of the digraph representation of the circuit. Next, the problem of the increased switching power, which results from driving all inputs to a given state when entering the standby mode, is addressed. For a given upper bound B on the leakage, the MLS algorithm is extended to identify the maximal input cube with the minimum switching cost from the set of minterms whose maximum leakage is lesB. The switching cost associated with an input is taken to be proportional to the load capacitance of that input. The algorithms have been successfully tested on the ISCAS85 and MCNC91 benchmark circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Frequency-Domain Simulation of Ring Oscillators With a Multiple-Probe Method

    Publication Year: 2006 , Page(s): 2833 - 2842
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (738 KB)  

    A new multiple-probe method is presented for the simulation of highly nonlinear ring oscillators using the harmonic-balance method. This method is robust compared to the conventional single-probe method and readily converges for a wide range of single-ended and differential ring oscillators. Furthermore, it is computationally more efficient for ring oscillators in which the conventional single-probe method converges View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Robust Simulation of High-Q Oscillators Using a Homotopy-Based Harmonic Balance Method

    Publication Year: 2006 , Page(s): 2843 - 2851
    Cited by:  Papers (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (337 KB) |  | HTML iconHTML  

    The simulation of high-Q oscillators in the frequency domain is difficult due to a very small region of convergence. In this paper, globally convergent homotopy methods are combined with the harmonic balance method for simulation of high-Q oscillators. Various homotopy options have been evaluated, and an algorithm has been developed that is robust in simulating a wide range of oscillator circuits View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • Statistical Sampling-Based Parametric Analysis of Power Grids

    Publication Year: 2006 , Page(s): 2852 - 2867
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1086 KB) |  | HTML iconHTML  

    A statistical sampling-based parametric analysis is presented for analyzing large power grids in a "localized" fashion. By combining random walks with the notion of "importance sampling," the proposed technique is capable of efficiently computing the impacts of multiple circuit parameters on selected network nodes. A "new localized" sensitivity analysis is first proposed to solve not only the nominal node response but also its sensitivities with respect to multiple parameters using a single run of the random walks algorithm. This sampling-based technique is further extended from the first-order sensitivity analysis to a more general second-order analysis. By exploiting the natural spatial locality inherent in the proposed algorithm formulation, the second-order analysis can be performed efficiently even for a large number of global and local variation sources. The theoretical convergence properties of three importance sampling estimators for power grid analysis are presented, and their effectiveness is compared experimentally on several examples. The superior performance of the proposed technique is demonstrated by analyzing several large power grids under process and current loading variations to which the application of the existing brute-force simulation techniques becomes completely infeasible View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.
  • A Quasi-Newton Preconditioned Newton–Krylov Method for Robust and Efficient Time-Domain Simulation of Integrated Circuits With Strong Parasitic Couplings

    Publication Year: 2006 , Page(s): 2868 - 2881
    Cited by:  Papers (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (936 KB) |  | HTML iconHTML  

    In this paper, the Newton-Krylov method is explored for robust and efficient time-domain simulation of integrated circuits with large amount of parasitic elements. Different from LU-factorization-based direct methods used in SPICE-like circuit simulators, the Newton-Krylov method uses a preconditioned Krylov-subspace iterative method for solving linearized-circuit equations. A key contribution of this paper is to introduce an effective quasi-Newton preconditioning scheme for Krylov-subspace methods to reduce the number and cost of LU factorization during an entire time-domain circuit simulation. The proposed quasi-Newton preconditioning scheme consists of four key techniques: 1) a systematic method for adaptively controlling time step sizes; 2) automatically generated piecewise weakly nonlinear (PWNL) definition of nonlinear devices to construct quasi-Newton preconditioners; 3) low-rank update techniques for incrementally updating preconditioners; and 4) incomplete-LU preconditioning for efficiency. Experimental results on a collection of digital, analog, and RF circuits have shown that the quasi-Newton preconditioned Krylov-subspace method is as robust and accurate as the direct method used in SPICE. The proposed Newton-Krylov method is attractive for simulating circuits with massive parasitic RLC elements for postlayout verification. For a nonlinear circuit with power/ground networks with tens-of-thousand elements, the CPU time speedup over SPICE3 is over 20X, and it is expected to increase further with the circuit size View full abstract»

    Full text access may be available. Click article title to sign in or learn about subscription options.

Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the areas of computer-aided design of integrated circuits and systems.

Full Aims & Scope

Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu