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Circuits and Systems II: Express Briefs, IEEE Transactions on

Issue 11 • Date Nov. 2006

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Displaying Results 1 - 25 of 41
  • Table of contents

    Publication Year: 2006 , Page(s): C1 - C4
    Cited by:  Papers (1)
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    Freely Available from IEEE
  • IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

    Publication Year: 2006 , Page(s): C2
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  • Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers

    Publication Year: 2006 , Page(s): 1165 - 1169
    Cited by:  Papers (9)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (188 KB) |  | HTML iconHTML  

    A methodology to design high-speed power-efficient MOS current-mode logic (MCML) static frequency dividers is proposed. Analytical criteria to exploit the speed potential of MCML gates are first introduced. Then, an analytical strategy is formulated to progressively reduce the bias currents through the stages without affecting the divider operation speed, thereby reducing the overall power consumption. The proposed design approach is general and independent of the process adopted. Due to its simplicity, it can be used in a pencil-and-paper approach, avoiding a tedious and time-consuming trial-and-error approach based on simulations. Moreover, the analytical approach allows for a deeper understanding of the power-delay tradeoff involved in the design. As a design example, a 1:8 frequency divider is designed and simulated by using a 0.18-mum CMOS process View full abstract»

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  • Exploiting Hysteresys in MCML Circuits

    Publication Year: 2006 , Page(s): 1170 - 1174
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (156 KB) |  | HTML iconHTML  

    In this brief, hysteresis is introduced to improve the noise margin of positive-feedback source-coupled logic (PFSCL) gates, that are a modification of MOS current-mode logic recently proposed by the same authors. To better understand the effect of hysteresis on the performance and the design of these circuits, a simple analytical model of the noise margin is developed. Extensive simulations on a 0.18-mum CMOS process confirm the adequate accuracy of the model. The noise margin improvement due to the hysteresis is then exploited to reduce the logic swing, which can be beneficial in terms of the speed performance or the power consumption. Practical cases where hysteresis is advantageous are identified, and a comparison with PFSCL gates without hysteresis is carried out. Simulations confirm that, in some well-defined cases, hysteresis can significantly reduce the gate delay under a power constraint, or achieve a power saving under a speed constraint. As a fundamental result, hysteresis turns out to be an interesting design option to improve the power efficiency of PFSCL gates View full abstract»

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  • Quasi Rail-to-Rail Very Low-Voltage OPAMP With a Single pMOS Input Differential Pair

    Publication Year: 2006 , Page(s): 1175 - 1179
    Cited by:  Papers (6)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (384 KB) |  | HTML iconHTML  

    In this brief, a quasi-rail-to-rail low-voltage operational amplifier (VDD-VSS-VDSATP-VDSATN ) is introduced. A common-mode adapter that uses the common-mode voltage present at the common-source node of the available differential pair to accommodate the large common-mode input signal is proposed. The common-mode adapter operates properly at 300 kHz while driving a load capacitor of 15 pF and employs only 95 muW of static power. The amplifier was fabricated in a standard AMI 0.5-mum CMOS process (Vtn=0.7 V and Vtp=-0.9 V) and achieves an IM3 of - 48 dB at 300 kHz for a two-tone input signal of 0.8 Vpk-pk. A 1-V total supply voltage was used View full abstract»

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  • Accurate, Compact, and Power-Efficient Li-Ion Battery Charger Circuit

    Publication Year: 2006 , Page(s): 1180 - 1184
    Cited by:  Papers (51)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (938 KB) |  | HTML iconHTML  

    A novel, accurate, compact, and power-efficient lithium-ion (Li-Ion) battery charger designed to yield maximum capacity, cycle life, and therefore runtime is presented and experimentally verified. The proposed charger uses a diode to smoothly (i.e., continuously) transition between two high-gain linear feedback loops and control a single power MOS device, automatically charging the battery with constant current and then constant voltage. An adaptive power-efficient charging scheme in the form of a cascaded switching regulator supply ensures the voltage across the charging power-intensive pMOS remains low, thereby reducing its power losses and yielding up to 27% better overall power efficiency. An 83% power-efficient printed circuit board prototype was built and used to charge several Li-Ion batteries to within plusmn0.43% of their optimum full-charge voltage and therefore within a negligibly small fraction of their full capacity View full abstract»

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  • Some Simple Synchronization Criteria for Complex Dynamical Networks

    Publication Year: 2006 , Page(s): 1185 - 1189
    Cited by:  Papers (22)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (202 KB) |  | HTML iconHTML  

    Based on the concept of matrix measure, some simple synchronization criteria for complex dynamical networks are provided. If the coupling strength and the largest nonzero eigenvalue of the coupling matrix satisfy certain conditions, the stability of the synchronization manifold can be ensured. Furthermore, the proposed criteria are less conservative than some existing criteria View full abstract»

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  • Compensation of Loudspeaker Nonlinearity in Acoustic Echo Cancellation Using Raised-Cosine Function

    Publication Year: 2006 , Page(s): 1190 - 1194
    Cited by:  Papers (17)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (477 KB) |  | HTML iconHTML  

    The nonlinearity of a power amplifier or loudspeaker in a large-signal situation gives rise to a nonlinear distortion of acoustic signal. A conventional acoustic echo canceller using linear adaptive filters is not able to eliminate the nonlinear echo component. In this brief, a novel nonlinear echo cancellation technique is presented by using a nonlinear transformation in conjunction with a conventional linear adaptive filter. The nonlinear transformation is derived from a raised-cosine function and is exploited to compensate for the nonlinearity of a loudspeaker. The transformation parameters are updated using the normalized least mean square algorithm according to the unknown nonlinear characteristic of the loudspeaker. Computer simulations show that the proposed method yields, in general, a satisfactory cancellation performance while having a very low computational complexity View full abstract»

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  • Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs

    Publication Year: 2006 , Page(s): 1195 - 1199
    Cited by:  Papers (33)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (281 KB) |  | HTML iconHTML  

    Due to the presence of a binary phase detector (BPD) in the loop, bang-bang phase-locked loops (BBPLLs) are hard nonlinear systems. Since the BPD is usually also the only nonlinear element in the loop, in practical applications, BBPLLs are commonly analyzed by first linearizing the BPD and then using the traditional mathematical techniques for linear systems. To the author's knowledge, in the literature, the gain of the linearized BPD (Kbpd) is determined neglecting the effect of the BBPLL dynamics on the effective jitter seen by the BPD. In this brief, we develop an approach to the determination of Kbpd which takes into consideration also this effect. The approach is based on modeling the dynamics of a BBPLL as a Markov chain. This approach gives new insights into the behavior of the BBPLL and leads to an expression for the Kbpd, which is more general than the one currently known in literature View full abstract»

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  • Gain Calibration Technique for Increased Resolution in FRC Data Converters

    Publication Year: 2006 , Page(s): 1200 - 1204
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (451 KB) |  | HTML iconHTML  

    A feedforward residue compensation (FRC) data converter combines the benefits of a Nyquist rate analog-to-digital converter (ADC) with an oversampled converter. In this brief, the authors introduce a digital calibration technique that allows the FRC architecture to provide high resolution at high input signal frequencies. A high-performance pipeline ADC is used as an auxiliary converter to measure the quantization effects of an oversampled primary converter in the FRC architecture. A practical ADC architecture using a digital gain error calibration technique produces a 15-bit 70-Msample/s converter with greater than 100-dB spurious-free dynamic range. Simulation results are used to validate the architecture and gain calibration technique View full abstract»

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  • A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction

    Publication Year: 2006 , Page(s): 1205 - 1209
    Cited by:  Papers (26)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (618 KB) |  | HTML iconHTML  

    A low phase noise, delay-locked loop-based programmable frequency multiplier, with the multiplication ratio from 13 to 20 and output frequency range from 900 MHz to 2.9 GHz, is reported in this brief. A new switching control scheme is employed in the circuit to enable the capability of locking to frequencies either above or below the start-up frequency without initialization. To reduce the spurious output power level, a low-bandwidth auxiliary loop [period error compensation loop (PECL)] is employed to compensate for the output period error caused by the phase realignment errors. This frequency multiplier is implemented in TSMC 0.18-mum CMOS technology and measured with a synthesized frequency source. A significant reduction of the output spurs from -23 to -46.5 dB at 1.216 GHz is achieved by enabling the PECL. The measured cycle-to-cycle timing jitter at 2.16 GHz is 1.6 ps (rms) and 12.9 ps (pk-pk), and the phase noise is -110 dBc/Hz at 100-kHz offset with a power consumption of 19.8 mW at a 1.8-V power supply View full abstract»

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  • CMOS Image Sensors With Self-Powered Generation Capability

    Publication Year: 2006 , Page(s): 1210 - 1214
    Cited by:  Papers (16)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (941 KB) |  | HTML iconHTML  

    Considerations for CMOS image sensors with self-power generation capability design are presented. Design of CMOS imagers, utilizing self-powered sensors (SPS) is a new approach for ultra low-power CMOS active pixel sensors (APS) implementations. The SPS architecture allows generation of electric power by employing a light sensitive device, located on the same silicon die with an APS and thus reduces power dissipation from the conventional power supply. A detailed analysis of the SPS structure is carried out, with respect to power dissipation requirements, sensor area and power generation efficiency, showing advantages and drawbacks of the proposed concept. An illustrative example of CMOS imager with self-power generation capability in 0.18-mum standard CMOS technology is discussed. Measurements from a test chip, implemented in 0.18-mum CMOS process, are presented View full abstract»

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  • Subthreshold Operation of a Monolithically Integrated Strained-Si Current Mirror at Low Temperatures

    Publication Year: 2006 , Page(s): 1215 - 1219
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (294 KB) |  | HTML iconHTML  

    The dc operation of a simple current mirror built with two monolithically integrated strained-Si (s-Si) MOSFETs operating in the subthreshold region is studied as a function of temperature. At room temperature, the log-log current relationship is linear over 4 dec. The consumed power is approximately 100 muW at 300 K but only 1 nW at 160 K. The cost of this reduction in power is a reduced linear log-log current range. Reducing the temperature further increases the threshold voltage, obstructing operation below 160 K. A comparison is made with the Si control circuit, highlighting the improved linearity and the threshold voltage stability in the s-Si circuit. The estimated cutoff frequency of the subthreshold strained-Si current mirror at 300 K is 50 MHz, compared to 10 kHz for the Si MOSFETs View full abstract»

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  • Finite Horizon {H}^{\infty } Filtering With Initial Condition

    Publication Year: 2006 , Page(s): 1220 - 1224
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (175 KB) |  | HTML iconHTML  

    We consider the problem of finite horizon Hinfin filtering with uncertain initial conditions. An Hinfin norm-like performance measure that explicitly accounts for the effect of initial condition is proposed. Necessary and sufficient conditions are derived for the existence of an estimator that achieves a pre-specified value of this performance measure View full abstract»

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  • The Analytic Determination of the PPV for Second-Order Oscillators Via Time-Varying Eigenvalues

    Publication Year: 2006 , Page(s): 1225 - 1229
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (139 KB) |  | HTML iconHTML  

    Time-varying eigenvalues may be used to formulate a set of linearly independent solutions for an arbitrary dynamical linear time-varying system. In this brief, it is shown how these quantities are used to determine analytically the perturbation projection vector (PPV) associated to a given oscillator. The PPV can be further used to estimate the spectral and timing properties of the oscillator output subject to the presence of noise sources. For this purpose, a complete set of solutions of the variational system associated to the oscillator under consideration is generated in terms of time-varying eigenvalues. To compute these quantities, a solution for a particular form of the Riccati equation must be found. It is shown how to obtain a solution for this equation from the steady-state behavior of the oscillator. A simple example demonstrating the application of the concepts mentioned above is also provided View full abstract»

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  • A Study of the Optimal Data Rate for Minimum Power of I/Os

    Publication Year: 2006 , Page(s): 1230 - 1234
    Cited by:  Papers (4)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (175 KB) |  | HTML iconHTML  

    Power dissipation of multi-gigabit per second parallel input-output (I/O) links is an integral part of total integrated circuits (IC) power dissipation. This brief presents an optimal data rate per I/O link at which the power dissipation is minimized. The data rate is expressed as a function of the transmission channel's frequency response. The impact of considering the power due to on-chip electronic switching depends on the process technology of the IC. The analysis results show that an upper bound for the data rate exists based on the channel's frequency response and that the upper bound is being approached with more advanced process technologies View full abstract»

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  • An Improved Hα Filter Design for Systems With Time-Varying Interval Delay

    Publication Year: 2006 , Page(s): 1235 - 1239
    Cited by:  Papers (21)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (166 KB) |  | HTML iconHTML  

    This brief is concerned with Hinfin filter design for systems with time-varying interval delay (i.e., the time delay is varying in an interval). An appropriate type of Lyapunov functionals is proposed to investigate the delay-dependent Hinfin filter design problem. Improved delay-dependent results are presented by taking into account the interval range. Finally, a numerical example is given to demonstrate the effectiveness and the benefits of the proposed method View full abstract»

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  • Nonlinear Behaviors of Bandpass Sigma–Delta Modulators With Stable System Matrices

    Publication Year: 2006 , Page(s): 1240 - 1244
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (588 KB) |  | HTML iconHTML  

    It has been established that a class of bandpass sigma-delta modulators may exhibit state space dynamics which are represented by elliptical or fractal patterns confined within trapezoidal regions when the system matrices are marginally stable. In this brief, it is found that fractal or irregular chaotic patterns may also be exhibited in the phase plane when the system matrices are strictly stable View full abstract»

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  • Area-Efficient VLSI Design of Reed–Solomon Decoder for 10GBase-LX4 Optical Communication Systems

    Publication Year: 2006 , Page(s): 1245 - 1249
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (822 KB) |  | HTML iconHTML  

    The Reed-Solomon (RS) code is a widely used forward error correction technique to cope with the channel impairments in fiber communication systems. The typical parallel RS architecture requires huge hardware cost to achieve very high speed transmission data rate for optical systems. This brief presents an area-efficient VLSI architecture of the RS decoder by using a novel just-in-time folding modified Euclidean algorithm (JIT-FMEA). The JIT-FMEA VLSI architecture can greatly reduce the hardware complexity by about 50% compared with the fully expanded parallel RS architecture. Meanwhile, it can achieve very high throughput rate for the 10Gbase-LX4 optical communication system. The proposed RS decoder architecture has been designed and implemented by using 0.18-mum CMOS standard cell technology at a supply voltage of 1.8 V. The post-layout simulation results show that the design requires only about 20 K gates and can achieve the data processing rate of 3.2 Gb/s at a clock frequency of 400 MHz View full abstract»

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  • A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power

    Publication Year: 2006 , Page(s): 1250 - 1254
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (690 KB) |  | HTML iconHTML  

    This brief presents a heterogeneous multicore embedded processor architecture designed to exceed performance of traditional embedded processors while reducing the power consumed compared to low-power embedded processors. At the heart of this architecture is a multicore very large instruction word (VLIW) containing homogeneous execution cores/functional units. Additionally, heterogeneous combinational hardware function cores are tightly integrated to the VLIW core providing an opportunity for improved performance and reduced energy consumption. Our processor has been synthesized for both a 90-nm Stratix II field-programmable gate array and a 160-nm cell-based application-specific integrated circuit from Oki each operating at a core frequency of 167 MHz. For selected multimedia and signal processing benchmarks, we show how this processor provides kernel performance improvements averaging 179X over an Intel StrongARM and 36X over an Intel XScale leading to application speedups averaging 30X over StrongARM and 10X over XScale View full abstract»

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  • On the Conversion Between Number Systems

    Publication Year: 2006 , Page(s): 1255 - 1258
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (115 KB) |  | HTML iconHTML  

    This brief revisits the problem of conversion between number systems and asks the following question: given a nonnegative decimal number d, what is the value of the digit at position j in the corresponding base b number? Thus, we do not require the knowledge of other digits except the one we are interested in. Accordingly, we present a conversion function that relates each digit in a base b system to the decimal value that is equal to the base b number in question. We also show some applications of this new algorithm in the areas of parallel computing and cryptography View full abstract»

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  • Adaptive Ratio-Size Gates for Minimum-Energy Operation

    Publication Year: 2006 , Page(s): 1259 - 1263
    Cited by:  Papers (17)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (287 KB) |  | HTML iconHTML  

    Minimum-energy operation is a function of the gate-size ratio at different values of the power supply. In this brief, circuit designs that are capable of responding to changes in the power supply voltage and adjusting the gate-size ratio accordingly for minimum-energy operation are presented. The dynamically adjustable gate-size ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operations. This translates to maximized noise margins over the whole range of the supply voltage. Simulation results show that the performance of the proposed circuits is superior to fixed gate sizes aimed at fixed-supply operation. The proposed adaptive gate circuit designs provide up to six times reduction in the power-delay product in comparison with the fixed-size gate. The proposed designs represent a complete solution for circuits that have to adapt to wide variations in the power supply while preserving relative characteristics View full abstract»

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  • Nyquist-Rate Current-Steering Digital-to-Analog Converters With Random Multiple Data-Weighted Averaging Technique and Q^{N} Rotated Walk Switching Scheme

    Publication Year: 2006 , Page(s): 1264 - 1268
    Cited by:  Papers (10)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (494 KB) |  | HTML iconHTML  

    In this brief, Nyquist-rate current-steering digital-to-analog converters (DACs) applying the random multiple data-weighted averaging (RMDWA) technique and the QN rotated walk switching scheme are proposed such that high spurious-free dynamic range (SFDR) and small maximum output error can be achieved without calibrations, which are area and power consuming. RMDWA suppresses the harmonics caused by element mismatches to gain high SFDR performance. Furthermore, QN rotated walk can lower the maximum output error when RMDWA and Q N rotated walk are employed simultaneously. Because the benefits of both dynamic element matching technique and switching scheme are obtained by the proposed DAC structure, the proposed structure can deliver smaller maximum output errors than traditional randomization techniques even if a low-cost small-area DAC with poor matching property is adopted View full abstract»

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  • A Low-Complexity Synchronizer for OFDM-Based UWB System

    Publication Year: 2006 , Page(s): 1269 - 1273
    Cited by:  Papers (8)  |  Patents (1)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (659 KB) |  | HTML iconHTML  

    In current ultra-wideband (UWB) baseband synchronizer approaches, the parallel architecture is used to achieve over 500 MSamples/s throughput requirement. Therefore achieving low power and less area becomes the challenge of UWB baseband design. In this paper, a low-complexity synchronizer combining data-partition-based correlation algorithms and dynamic-threshold design is proposed for orthogonal frequency division multiplexing based UWB system. It provides a methodology to reduce design complexity with an acceptable performance loss. Based on the data-partition algorithms, both single auto-correlator and moving-average-free matched filter are developed with 528 Msample/s throughput for the 480 Mb/s UWB design. Simulation results show the synchronization loss can be limited to 0.8-dB signal-to-noise ratio for 8% system packet-error rate View full abstract»

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  • Current-Mode Monostable Multivibrators Using OTRAs

    Publication Year: 2006 , Page(s): 1274 - 1278
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (208 KB) |  | HTML iconHTML  

    Three nonretriggerable current-mode monostable multivibrators constructed of one operational transresistance amplifier (OTRA) and a few passive elements are presented in this brief. Two of these circuits are operated respectively under positive and negative triggering modes. However, the recovery time cannot be adjusted once the pulsewidth is decided. The third topology, which can work in either triggering mode, features a tunable recovery time. The proposed current-mode monostables are simpler compared to their counterparts composed of operational amplifiers. The circuit operations are described in detail. Experimental results are in good agreement with the theoretical analysis View full abstract»

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Aims & Scope

TCAS II publishes brief papers in the field specified by the theory, analysis, design, and practical implementations of circuits, and the application of circuit techniques to systems and to signal processing. Included is the whole spectrum from basic scientific theory to industrial applications. The field of interest covered includes:

  • Circuits: Analog, Digital and Mixed Signal Circuits and Systems  
  • Nonlinear Circuits and Systems, Integrated Sensors, MEMS and Systems on Chip, Nanoscale Circuits and Systems, Optoelectronic
  • Circuits and Systems, Power Electronics and Systems
  • Software for Analog-and-Logic Circuits and Systems
  • Control aspects of Circuits and Systems. 

Full Aims & Scope