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# IEEE Transactions on Circuits and Systems II: Express Briefs

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Displaying Results 1 - 25 of 41

Publication Year: 2006, Page(s):C1 - C4
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• ### IEEE Transactions on Circuits and Systems—II: Express Briefs publication information

Publication Year: 2006, Page(s): C2
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• ### Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers

Publication Year: 2006, Page(s):1165 - 1169
Cited by:  Papers (20)  |  Patents (1)
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A methodology to design high-speed power-efficient MOS current-mode logic (MCML) static frequency dividers is proposed. Analytical criteria to exploit the speed potential of MCML gates are first introduced. Then, an analytical strategy is formulated to progressively reduce the bias currents through the stages without affecting the divider operation speed, thereby reducing the overall power consump... View full abstract»

• ### Exploiting Hysteresys in MCML Circuits

Publication Year: 2006, Page(s):1170 - 1174
Cited by:  Papers (7)
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In this brief, hysteresis is introduced to improve the noise margin of positive-feedback source-coupled logic (PFSCL) gates, that are a modification of MOS current-mode logic recently proposed by the same authors. To better understand the effect of hysteresis on the performance and the design of these circuits, a simple analytical model of the noise margin is developed. Extensive simulations on a ... View full abstract»

• ### Quasi Rail-to-Rail Very Low-Voltage OPAMP With a Single pMOS Input Differential Pair

Publication Year: 2006, Page(s):1175 - 1179
Cited by:  Papers (18)
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In this brief, a quasi-rail-to-rail low-voltage operational amplifier (VDD-VSS-VDSATP-VDSATN ) is introduced. A common-mode adapter that uses the common-mode voltage present at the common-source node of the available differential pair to accommodate the large common-mode input signal is proposed. The common-mode adapter operates properly at 300 kHz while... View full abstract»

• ### Accurate, Compact, and Power-Efficient Li-Ion Battery Charger Circuit

Publication Year: 2006, Page(s):1180 - 1184
Cited by:  Papers (81)  |  Patents (1)
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A novel, accurate, compact, and power-efficient lithium-ion (Li-Ion) battery charger designed to yield maximum capacity, cycle life, and therefore runtime is presented and experimentally verified. The proposed charger uses a diode to smoothly (i.e., continuously) transition between two high-gain linear feedback loops and control a single power MOS device, automatically charging the battery with co... View full abstract»

• ### Some Simple Synchronization Criteria for Complex Dynamical Networks

Publication Year: 2006, Page(s):1185 - 1189
Cited by:  Papers (61)
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Based on the concept of matrix measure, some simple synchronization criteria for complex dynamical networks are provided. If the coupling strength and the largest nonzero eigenvalue of the coupling matrix satisfy certain conditions, the stability of the synchronization manifold can be ensured. Furthermore, the proposed criteria are less conservative than some existing criteria View full abstract»

• ### Compensation of Loudspeaker Nonlinearity in Acoustic Echo Cancellation Using Raised-Cosine Function

Publication Year: 2006, Page(s):1190 - 1194
Cited by:  Papers (25)  |  Patents (3)
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The nonlinearity of a power amplifier or loudspeaker in a large-signal situation gives rise to a nonlinear distortion of acoustic signal. A conventional acoustic echo canceller using linear adaptive filters is not able to eliminate the nonlinear echo component. In this brief, a novel nonlinear echo cancellation technique is presented by using a nonlinear transformation in conjunction with a conven... View full abstract»

• ### Markov Chains-Based Derivation of the Phase Detector Gain in Bang-Bang PLLs

Publication Year: 2006, Page(s):1195 - 1199
Cited by:  Papers (53)
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Due to the presence of a binary phase detector (BPD) in the loop, bang-bang phase-locked loops (BBPLLs) are hard nonlinear systems. Since the BPD is usually also the only nonlinear element in the loop, in practical applications, BBPLLs are commonly analyzed by first linearizing the BPD and then using the traditional mathematical techniques for linear systems. To the author's knowledge, in the lite... View full abstract»

• ### Gain Calibration Technique for Increased Resolution in FRC Data Converters

Publication Year: 2006, Page(s):1200 - 1204
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A feedforward residue compensation (FRC) data converter combines the benefits of a Nyquist rate analog-to-digital converter (ADC) with an oversampled converter. In this brief, the authors introduce a digital calibration technique that allows the FRC architecture to provide high resolution at high input signal frequencies. A high-performance pipeline ADC is used as an auxiliary converter to measure... View full abstract»

• ### A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction

Publication Year: 2006, Page(s):1205 - 1209
Cited by:  Papers (40)
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A low phase noise, delay-locked loop-based programmable frequency multiplier, with the multiplication ratio from 13 to 20 and output frequency range from 900 MHz to 2.9 GHz, is reported in this brief. A new switching control scheme is employed in the circuit to enable the capability of locking to frequencies either above or below the start-up frequency without initialization. To reduce the spuriou... View full abstract»

• ### CMOS Image Sensors With Self-Powered Generation Capability

Publication Year: 2006, Page(s):1210 - 1214
Cited by:  Papers (30)  |  Patents (4)
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Considerations for CMOS image sensors with self-power generation capability design are presented. Design of CMOS imagers, utilizing self-powered sensors (SPS) is a new approach for ultra low-power CMOS active pixel sensors (APS) implementations. The SPS architecture allows generation of electric power by employing a light sensitive device, located on the same silicon die with an APS and thus reduc... View full abstract»

• ### Subthreshold Operation of a Monolithically Integrated Strained-Si Current Mirror at Low Temperatures

Publication Year: 2006, Page(s):1215 - 1219
Cited by:  Papers (1)
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The dc operation of a simple current mirror built with two monolithically integrated strained-Si (s-Si) MOSFETs operating in the subthreshold region is studied as a function of temperature. At room temperature, the log-log current relationship is linear over 4 dec. The consumed power is approximately 100 muW at 300 K but only 1 nW at 160 K. The cost of this reduction in power is a reduced linear l... View full abstract»

• ### Finite Horizon ${H}^{infty}$ Filtering With Initial Condition

Publication Year: 2006, Page(s):1220 - 1224
Cited by:  Papers (4)
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We consider the problem of finite horizon Hinfin filtering with uncertain initial conditions. An Hinfin norm-like performance measure that explicitly accounts for the effect of initial condition is proposed. Necessary and sufficient conditions are derived for the existence of an estimator that achieves a pre-specified value of this performance measure View full abstract»

• ### The Analytic Determination of the PPV for Second-Order Oscillators Via Time-Varying Eigenvalues

Publication Year: 2006, Page(s):1225 - 1229
Cited by:  Papers (3)
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Time-varying eigenvalues may be used to formulate a set of linearly independent solutions for an arbitrary dynamical linear time-varying system. In this brief, it is shown how these quantities are used to determine analytically the perturbation projection vector (PPV) associated to a given oscillator. The PPV can be further used to estimate the spectral and timing properties of the oscillator outp... View full abstract»

• ### A Study of the Optimal Data Rate for Minimum Power of I/Os

Publication Year: 2006, Page(s):1230 - 1234
Cited by:  Papers (6)  |  Patents (2)
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Power dissipation of multi-gigabit per second parallel input-output (I/O) links is an integral part of total integrated circuits (IC) power dissipation. This brief presents an optimal data rate per I/O link at which the power dissipation is minimized. The data rate is expressed as a function of the transmission channel's frequency response. The impact of considering the power due to on-chip electr... View full abstract»

• ### An Improved Hα Filter Design for Systems With Time-Varying Interval Delay

Publication Year: 2006, Page(s):1235 - 1239
Cited by:  Papers (94)
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This brief is concerned with Hinfin filter design for systems with time-varying interval delay (i.e., the time delay is varying in an interval). An appropriate type of Lyapunov functionals is proposed to investigate the delay-dependent Hinfin filter design problem. Improved delay-dependent results are presented by taking into account the interval range. Finally, a numerical e... View full abstract»

• ### Nonlinear Behaviors of Bandpass Sigma–Delta Modulators With Stable System Matrices

Publication Year: 2006, Page(s):1240 - 1244
Cited by:  Papers (4)
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It has been established that a class of bandpass sigma-delta modulators may exhibit state space dynamics which are represented by elliptical or fractal patterns confined within trapezoidal regions when the system matrices are marginally stable. In this brief, it is found that fractal or irregular chaotic patterns may also be exhibited in the phase plane when the system matrices are strictly stable View full abstract»

• ### Area-Efficient VLSI Design of Reed–Solomon Decoder for 10GBase-LX4 Optical Communication Systems

Publication Year: 2006, Page(s):1245 - 1249
Cited by:  Papers (25)
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The Reed-Solomon (RS) code is a widely used forward error correction technique to cope with the channel impairments in fiber communication systems. The typical parallel RS architecture requires huge hardware cost to achieve very high speed transmission data rate for optical systems. This brief presents an area-efficient VLSI architecture of the RS decoder by using a novel just-in-time folding modi... View full abstract»

• ### A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power

Publication Year: 2006, Page(s):1250 - 1254
Cited by:  Papers (5)
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This brief presents a heterogeneous multicore embedded processor architecture designed to exceed performance of traditional embedded processors while reducing the power consumed compared to low-power embedded processors. At the heart of this architecture is a multicore very large instruction word (VLIW) containing homogeneous execution cores/functional units. Additionally, heterogeneous combinatio... View full abstract»

• ### On the Conversion Between Number Systems

Publication Year: 2006, Page(s):1255 - 1258
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This brief revisits the problem of conversion between number systems and asks the following question: given a nonnegative decimal number d, what is the value of the digit at position j in the corresponding base b number? Thus, we do not require the knowledge of other digits except the one we are interested in. Accordingly, we present a conversion function that relates each digit in a base b system... View full abstract»

• ### Adaptive Ratio-Size Gates for Minimum-Energy Operation

Publication Year: 2006, Page(s):1259 - 1263
Cited by:  Papers (26)
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Minimum-energy operation is a function of the gate-size ratio at different values of the power supply. In this brief, circuit designs that are capable of responding to changes in the power supply voltage and adjusting the gate-size ratio accordingly for minimum-energy operation are presented. The dynamically adjustable gate-size ratio allows the gate to preserve a symmetric voltage transfer charac... View full abstract»

• ### Nyquist-Rate Current-Steering Digital-to-Analog Converters With Random Multiple Data-Weighted Averaging Technique and $Q^{N}$ Rotated Walk Switching Scheme

Publication Year: 2006, Page(s):1264 - 1268
Cited by:  Papers (16)  |  Patents (4)
| | PDF (494 KB) | HTML

In this brief, Nyquist-rate current-steering digital-to-analog converters (DACs) applying the random multiple data-weighted averaging (RMDWA) technique and the QN rotated walk switching scheme are proposed such that high spurious-free dynamic range (SFDR) and small maximum output error can be achieved without calibrations, which are area and power consuming. RMDWA suppresses the harmoni... View full abstract»

• ### A Low-Complexity Synchronizer for OFDM-Based UWB System

Publication Year: 2006, Page(s):1269 - 1273
Cited by:  Papers (15)  |  Patents (1)
| | PDF (659 KB) | HTML

In current ultra-wideband (UWB) baseband synchronizer approaches, the parallel architecture is used to achieve over 500 MSamples/s throughput requirement. Therefore achieving low power and less area becomes the challenge of UWB baseband design. In this paper, a low-complexity synchronizer combining data-partition-based correlation algorithms and dynamic-threshold design is proposed for orthogonal ... View full abstract»

• ### Current-Mode Monostable Multivibrators Using OTRAs

Publication Year: 2006, Page(s):1274 - 1278
Cited by:  Papers (22)
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Three nonretriggerable current-mode monostable multivibrators constructed of one operational transresistance amplifier (OTRA) and a few passive elements are presented in this brief. Two of these circuits are operated respectively under positive and negative triggering modes. However, the recovery time cannot be adjusted once the pulsewidth is decided. The third topology, which can work in either t... View full abstract»

## Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Chi K. Michael Tse
Dept. of Electronic and Information Engineering
Hong Kong Polytechnic University
Hunghom, Hong Kong
cktse@ieee.org