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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Issue 8 • Date Aug 1992

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Displaying Results 1 - 10 of 10
  • Coupling algorithms for mixed-level circuit and device simulation

    Publication Year: 1992, Page(s):1003 - 1012
    Cited by:  Papers (23)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (804 KB)

    A general framework for mixed-level circuit and device simulation is described. This framework was used in the development of the simulation program CODECS (coupled device and circuit simulator). Various algorithms to couple the device and circuit simulators for DC and transient analyses have been implemented in CODECS. These algorithms are evaluated based on their convergence properties and run-t... View full abstract»

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  • Optimal floorplan area optimization

    Publication Year: 1992, Page(s):992 - 1002
    Cited by:  Papers (36)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (892 KB)

    An optimal algorithm for the floorplan area optimization problem is presented. The algorithm is based on an extension of the technique of L. Stockmeyer (1983). Experimental results indicate that the authors' algorithm is efficient and capable of successfully handling large floor plans. The algorithm is compared with the branch-and-bound optimal algorithm of S. Wimer et al. (ibid., vol.8, no.2, p.1... View full abstract»

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  • An H-V alternating router

    Publication Year: 1992, Page(s):976 - 991
    Cited by:  Papers (11)  |  Patents (15)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (1264 KB)

    An H-V alternating router based on the concurrent H (horizontal) and V (vertical) tile expansions is presented. The router is modeled by a sequence of alternating H and V corner-stitching space tiles, where the expansion direction is controlled by a heuristic evaluation function using the A* technique and the damping concept. Tile growing is governed by the following three factors: constrained exp... View full abstract»

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  • On the assumptions contained in semiconductor yield models

    Publication Year: 1992, Page(s):966 - 975
    Cited by:  Papers (13)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (884 KB)

    It is shown that the form of semiconductor yield models, and their predictions, are to a large extent affected by the size distribution of all defects and the spatial distribution of fatal defects. As the effects of these and other assumptions on yield models are rarely described in the literature, the author examines them and develops scaling rules for the average number of fatal defects per chip... View full abstract»

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  • Predicting system-level area and delay for pipelined and nonpipelined designs

    Publication Year: 1992, Page(s):955 - 965
    Cited by:  Papers (39)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (892 KB)

    The ability to predict area-delay characteristics of designs without actually implementing them is important in producing quality designs in a reasonable time. A mathematical model for predicting the area-delay tradeoff curve for pipelined and nonpipelined data paths, given a data flow graph and a choice of module styles, is proposed. The model has been validated against designs generated by pipel... View full abstract»

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  • PLADE: a two-stage PLA decomposition

    Publication Year: 1992, Page(s):943 - 954
    Cited by:  Papers (11)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (960 KB)

    An efficient method for PLA decomposition, in which a single two-level Boolean function (PLA) is decomposed into two stages of cascaded PLAs such that the total area of all PLAs is smaller than that of the original PLA, is presented. The first stage may contain an arbitrary number of PLAs (generalized decoders), and the second stage contains a single PLA. Primary inputs are partitioned into disjoi... View full abstract»

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  • A performance-driven global router for custom VLSI chip design

    Publication Year: 1992, Page(s):1044 - 1051
    Cited by:  Papers (5)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (624 KB)

    A performance-driven global router for custom VLSI chip design, with the objective of maximizing the minimum delay slack, is presented. Resistances and capacitances of interconnections, input gate capacitances, and output driver resistance are used to approximate the interconnection delays during the routing. The router incrementally updates the delay at each sink pin of the signal obtained from t... View full abstract»

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  • An explicit method of numerical integration for the complete set of semiconductor device equations

    Publication Year: 1992, Page(s):1013 - 1023
    Cited by:  Papers (1)  |  Patents (1)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (752 KB)

    A method is developed for solving the complete set of semiconductor device equations, based on the explicit method of integration with the characteristic features that time derivatives and spatially dependent intervals for the integration in time are introduced. Determination of the time intervals, which are of decisive importance for the method to converge, is made theoretically on the basis of t... View full abstract»

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  • HALO: an efficient global placement strategy for standard cells

    Publication Year: 1992, Page(s):1024 - 1031
    Cited by:  Papers (4)  |  Patents (4)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (680 KB)

    A standard cell placement procedure that is based on an efficient global placement strategy, called HALO (hierarchical alternating liner ordering), is proposed. This method generates a global 2D placement of circuit modules by hierarchical application of linear ordering in an alternating direction. The HALO global placement procedure is followed by a detailed placement procedure which consists of ... View full abstract»

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  • Mixed frequency/time domain analysis of nonlinear circuits

    Publication Year: 1992, Page(s):1032 - 1043
    Cited by:  Papers (37)  |  Patents (3)
    Request permission for commercial reuse | Click to expandAbstract | PDF file iconPDF (824 KB)

    A method for the transient analysis of nonlinear circuits with frequency-dependent parameters is described. This method does not require numerical integration of differential equations. Applications include delay and crosstalk simulation of high-speed VLSI interconnects and simulation of nonlinear microwave circuits with parameters calculated or measured as a function of frequency. Examples and co... View full abstract»

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Aims & Scope

The purpose of this Transactions is to publish papers of interest to individuals in the area of computer-aided design of integrated circuits and systems composed of analog, digital, mixed-signal, optical, or microwave components.

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Meet Our Editors

Editor-in-Chief

VIJAYKRISHNAN NARAYANAN
Pennsylvania State University
Dept. of Computer Science. and Engineering
354D IST Building
University Park, PA 16802, USA
vijay@cse.psu.edu