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Solid-State Circuits, IEEE Journal of

Issue 8 • Date Aug 1992

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Displaying Results 1 - 13 of 13
  • Digitally adjustable resistors in CMOS for high-performance applications

    Publication Year: 1992 , Page(s): 1176 - 1185
    Cited by:  Papers (29)  |  Patents (112)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (820 KB)  

    Methods by which CMOS circuits can be adjusted digitally to generate controlled impedances for use in high-performance circuits are described. Since digital signals are the only inputs to these circuits, on-chip DC power dissipation can be reduced, the circuit can be made more robust, and the impedance of the circuit can be adjusted by manipulating the input digital information. A design of a CMOS series terminated line driver is discussed, and the utilization of the controlled impedance in terminating transmission lines on-chip, constant delay lines, and controlled di/dt output buffers is discussed View full abstract»

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  • A new resonant-tunnel diode-based multivalued memory circuit using a MESFET depletion load

    Publication Year: 1992 , Page(s): 1198 - 1202
    Cited by:  Papers (13)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (360 KB)  

    A resonant-tunnel-diode-based (RTD-based) multivalued memory (MVM) circuit using a depletion-load MESFET is described. Compared with the commonly used resistor load in multivalued logic (MVL) circuits, this circuit design offers better noise margins, lower power dissipation, and easier integration. SPICE was used to simulate a three-state memory circuit, functioning as a MVL cell and consisting of a series connection of two RTDs and a MESFET depletion load. It is shown that the simulated multipeak I-V curve for this MVM cell is in good agreement with the measurement results from the two discrete RTDs connected in series. The signal write and read operations for this MVM circuit are also successfully simulated, and these operations were reliable and showed fast response. Some important effects on the MVM circuit due to the parasitic resistor and capacitor in the RTD are discussed. This MVM cell structure can be easily extended to implement more states in a memory circuit View full abstract»

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  • High-speed low-power ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage

    Publication Year: 1992 , Page(s): 1207 - 1210
    Cited by:  Papers (7)  |  Patents (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (308 KB)  

    The design of an ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array applications is presented. The circuit features an AC-coupled dynamic current source to improve the power-delay of the logic stage (current switch). A self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8-μm double-poly, self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 1.62× (1.90×) improvement in the speed (load driving capability) of a loaded gate compared with the conventional ECL circuit View full abstract»

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  • A 1-GHz single-chip quadrature modulator

    Publication Year: 1992 , Page(s): 1194 - 1197
    Cited by:  Papers (29)  |  Patents (7)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (340 KB)  

    The design of an integrated quadrature modulator for a 800-MHz to 1-GHz frequency range is presented. It is shown that this modulator achieves a phase error of less than ±3° without any trimming or tuning. This performance was achieved by reducing the number of building blocks and keeping a symmetrical transistor structure even in the layout. To overcome the amplitude difference of the phase-shifted signals, a modulator principle is used rather than a multiplier principle. The circuit was implemented in a bipolar transistor array with an fT of 9 GHz View full abstract»

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  • A large VDS data retention test pattern for DRAM's

    Publication Year: 1992 , Page(s): 1214 - 1217
    Cited by:  Papers (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (276 KB)  

    A test pattern for testing DRAM cell data retention that differs from conventional retention time tests is described. The test pattern is applicable to non-VDD bit-line precharge designs, and is specifically designed to test for worst-case subthreshold leakage through the cell access device by holding bit lines in their latched position for extended periods. This action stresses the cell access devices with the worst-case VDS across them. The reasons to perform this test on a DRAM are reviewed, its advantages over standard retention time tests are described, and its ability to differentiate access device leakage from isolation leakage is discussed. Measured results on a 1-Mb chip are shown, illustrating the test pattern's effectiveness in screening subthreshold leakage View full abstract»

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  • Totally self-checking CMOS circuit design for breaks and stuck-on faults

    Publication Year: 1992 , Page(s): 1203 - 1206
    Cited by:  Papers (3)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (244 KB)  

    A technique for designing totally self-checking FCMOS circuits is presented. Two types of defects have been considered: breaks (caused by missing conducting material or extra insulating material) and transistor stuck-on faults. In order to make FCMOS circuits totally self-checking for all breaks and transistor stuck-on faults, only four extra transistors need to be added to the functional circuit. The additional circuitry is added in such a way that for any break or transistor stuck-on defect in the functional circuit, the outputs assume a value of 01 or 10, respectively. The output of the defect-free circuit will be 11 (00) when the input pattern applied to the circuit connects V dd(GND) to the output node View full abstract»

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  • Synthesis techniques for CMOS folded source-coupled logic circuits

    Publication Year: 1992 , Page(s): 1157 - 1167
    Cited by:  Papers (26)  |  Patents (4)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (932 KB)  

    The application of series-gated, multiplexer-minimization, and variable-entered mapping methods to the synthesis of fully differential CMOS folded source-coupled logic (FSCL) gates is described. In contrast to conventional static logic, FSCL dissipates DC power. Its total power consumption is competitive at higher speeds where its low digital switching noise is most advantageous. The minimum propagation delay of a simple FSCL gate compares favorably to a conventional gate. Complex functions are generally faster in FSCL since its fully differential topology requires fewer stages of delay. Simulated and measured results are presented for several combinational and sequential FSCL gates in a 2-μm p-well CMOS process. With Vdd=5 V, a FSCL (static) inverter achieved a minimum propagation delay of 400 ps (350 ps) with a power-delay product of 0.5 pJ (0.3 pJ); a FSCL (static) 1-b full adder achieved a minimum delay of 3.0 ns (12.0 ns) with a power-delay product of 0.3 pJ (11.0 pJ) View full abstract»

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  • An analytical access time model for on-chip cache memories

    Publication Year: 1992 , Page(s): 1147 - 1156
    Cited by:  Papers (52)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (768 KB)  

    An analytical access time model for on-chip cache memories that shows the dependence of the cache access time on the cache parameters is described. The model includes general cache parameters, such as cache size (C), block size (B), and associativity (A), and array configuration parameters that are responsible for determining the subarray aspect ratio and the number of subarrays. With this model, a large cache design space can be covered, which cannot be done using only SPICE circuit simulation within a limited time. Using the model, it is shown that for given C, B, and A , optimum array configuration parameters can be used to minimize the access time; if the optimum array parameters are used, then the optimum access time is roughly proportional to the log (cache size), and when the optimum array parameters are used, larger block size gives smaller access time, but larger associativity does not give smaller access time because of the increase of the data-bus capacitances View full abstract»

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  • An offset reduction technique for use with CMOS integrated comparators and amplifiers

    Publication Year: 1992 , Page(s): 1168 - 1175
    Cited by:  Papers (24)  |  Patents (14)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (624 KB)  

    Methods for reducing the input offset voltage of comparators and amplifiers are reviewed. A comparator that adjusts its own offset either at power-up or in response to a control input is presented. The nature of the offset adjustment is such that the comparator is capable of continuous-time operation. Room-temperature offset in the range of -100 to +100 μV are achievable. Adjusted offsets exhibit a temperature coefficient on the order of -1 μV/°C View full abstract»

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  • A small-signal model for the frequency-dependent drain admittance in floating-substrate MOSFET's

    Publication Year: 1992 , Page(s): 1186 - 1193
    Cited by:  Papers (20)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (572 KB)  

    The frequency-dependent drain admittance of silicon-on-sapphire (SOS) MOSFETs is examined from the perspective of the circuit designer. Measurements of small-signal drain characteristics as a function of frequency, bias conditions, and device geometry, which have major implications for analog circuit design, are presented. These are explained in terms of a small-signal circuit model. Physical explanations for the observations are given and the poles and zeros of the model identified to assist designers carrying out hand calculations with easily manipulated expressions. Frequency-dependent thermal effects are discussed. It is shown that similar effects can be expected in other SOI technologies View full abstract»

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  • PLA design for single-clock CMOS

    Publication Year: 1992 , Page(s): 1211 - 1213
    Cited by:  Papers (16)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (240 KB)  

    The circuit implementation of a CMOS programmable logic array (PLA) is described for use with a single-phased clock, combining both dynamic and pseudo-NMOS design styles. Compact layout and high speed of operation is achieved with low static power dissipation. The circuit design, circuit speed, circuit layout, and timing diagram are presented View full abstract»

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  • A secondary cache controller design for a high-end microprocessor

    Publication Year: 1992 , Page(s): 1141 - 1146
    Cited by:  Papers (1)  |  Patents (5)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (516 KB)  

    The design of a CMOS cache controller chip for a high-end (i486) microprocessor is presented. The cache controller supports either two lines per tag (sectored) or one line per tag (nonsectored). A single cache controller directly supports nonsectored 64 kilobyte or sectored 128 kilobyte cache memories. The sectored mode effectively doubles the cache size compared to the nonsectored mode while maintaining the same tag RAM size. The cache controller is designed to be completely software transparent and contains a 4 K-tag entry tag RAM on-chip and supports burst read, burst line fill, snoop, and back-off cycles. Read-only spaces can also be cached with write protections. Two-way set associativity, sectored cache, and efficient cache protocols optimize performance of the cache memory system and complexity of the cache controller design. This chip supports a 25- or 33-MHz microprocessor. This high speed is achieved by dividing the tag RAM array into eight small sections, thus reducing the overall access time of the tag RAM View full abstract»

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  • Design and implementation of a 3D-LSI image sensing processor

    Publication Year: 1992 , Page(s): 1130 - 1140
    Cited by:  Papers (7)  |  Patents (2)
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1088 KB)  

    A four-story structured image sensing processor implemented with three-dimensional LSI (3D-LSI) technology and integrating 5040 pixel photodiodes and 0.22 million transistors on a 14.3-mm2 single die is described. The implemented chip allows a large degree of data parallelism in image computations where the image sensor unit operates without synchronous clocks. The chip, which is a second prototype, is able to sense 12 characters at the same time, and can recognize 64 different characters in upper and lower case, Arabic numerals, and some symbols, each consisting of a 10×14 matrix. The chip is made of a large number of simple processing elements working in parallel, which speeds up computation. The time needed to identify a sensed image as a memorized character is about 3 μs. Successful measurements of the principal functions verify the usefulness of the chip View full abstract»

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Aims & Scope

The IEEE Journal of Solid-State Circuits publishes papers each month in the broad area of solid-state circuits with particular emphasis on transistor-level design of integrated circuits.

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Meet Our Editors

Editor-in-Chief
Michael Flynn
University of Michigan