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Electron Devices, IEEE Transactions on

Issue 8 • Date Aug 1992

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Displaying Results 1 - 25 of 30
  • CMOS-compatible lateral bipolar transistor for BiCMOS technology. II. Experimental results

    Page(s): 1865 - 1869
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    For Pt.I see ibid., vol.39, no.4, p.948-51 (1992). Characteristics of a CMOS-compatible lateral bipolar transistor suitable for low-cost and high-speed BiCMOS LSIs are described. The proposed transistor has a structure analogous to that of the NMOS transistor, which employs a source and drain self-aligned structure to form an emitter and collector. The obtained values of hFE, BVCEO, R CS, fTmax, and rbb', are 20, 7 V, 50 Ω, 6.3 GHz, and 450 Ω, respectively. Moreover, delay times of a two-input NAND BiCMOS gate circuit are 0.28 ns when unloaded, and 0.42 and 0.53 ns when load capacitances are 1 and 2 pF, respectively. These values are comparable to those for BiCMOS circuits using the conventional vertical bipolar transistors View full abstract»

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  • Effects of interface traps on the transconductance and drain current of InP MISFET's

    Page(s): 1797 - 1804
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    The drain current, transconductance, and output resistance of an InP MISFET are shown to depend strongly on the frequency and amplitude of an AC signal applied to the gate. This dependence exists even though the familiar long-term current drift effect is negligible. To explain this phenomenon a new nonequilibrium interface-trap model is proposed View full abstract»

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  • CCM-a new low-noise charge carrier multiplier suitable for detection of charge in small pixel CCD image sensors

    Page(s): 1972 - 1975
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    A new charge detection concept, useful for small pixel CCD image sensors, where the collected signal carriers are first multiplied before charge is converted into an output voltage is described. The carrier multiplication is performed in a low-noise charge carrier multiplier (CCM) which is located in a CCD channel. The multiplication occurs during the charge transfer process and is externally controllable by suitably arranged device lateral fields View full abstract»

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  • Determination of space-dependent electron distribution function by combined use of energy and Boltzmann transport equations: improvement, evaluation, and explanation

    Page(s): 1821 - 1828
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    An improved extrapolation technique for obtaining space-dependent electron energy distribution functions by combining energy transport simulations with solutions to the homogeneous-field Boltzmann equation is presented. The accuracy of the method depends on two criteria. First, the validity of this method relies strongly on the accurate average energy, which is used as a vehicle for extrapolation and is ascertained by solving the energy balance equation. Second, the method should be applicable when the spatial variations of average energy are not appreciable over the distance of a mean free path. In light of the importance of the average energy, the details of application of the energy balance equation and their impact on the modeling of the distribution function are examined by comparison with the Monte Carlo calculations. An explanation for the success of the technique is presented. In addition to being efficient enough for daily use in device design, the method incorporates many of the physical details required for accurate analysis View full abstract»

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  • A new two-dimensional model for the potential distribution of short gate-length MESFET's and its applications

    Page(s): 1928 - 1937
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    A new analytical technique for calculating the 2-D potential distribution of a MESFET device operated in the subthreshold region is proposed, in which the 2-D Poisson's equation is solved by the Green's function technique. The potential and electric-field distributions of a non-self-aligned MESFET device are calculated exactly from different types of Green's function in different boundary regions, and the sidewall potential at the interface between these regions can be determined by the continuation of the electric field at the sidewall boundary. The remarkable feature of the proposed method is that the implanted doping profile in the active channel can be treated. Furthermore, a simplified technique is developed to derive a set of quasi-analytical models for the sidewall potential at both sides of the gate edge, the threshold voltage of short gate-length devices, and the drain-induced barrier lowering. Moreover, the developed quasi-analytical models are compared with the results of 2-D numerical analysis and good agreements are obtained View full abstract»

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  • Transient latchup characteristics in n-well CMOS

    Page(s): 1870 - 1875
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    Transient latchup characteristics in scaled n-well CMOS triggered by pulsewidths less than 10 ns are presented by experiments and two-dimensional device simulations. Vibratile increasing latchup currents predicted by the simulations are experimentally observed for the devices with the n+-p+ spacing L longer than 8 μm, and twin-peaks curves in supply currents just before latchup turn-on are also measured. Those experimental results are in relatively good agreement with the simulations triggered by a trapezoidal pulse. It is also reported that CMOS latchup susceptibilities to narrow trigger-pulse widths of less than 50 ns cannot be expected as L becomes as short as about 4 μm View full abstract»

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  • A study of radially thick helix: equivalent circuit approach

    Page(s): 1961 - 1965
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    An equivalent circuit analysis has been designed to study a radially thick helix to obtain various design parameters: capacitance per unit length, inductance per unit length, characteristic impedance, dispersion relation, and interaction impedance. This analysis does not require the solution of a complex determinantal dispersion relation as needed in field analysis. The analysis has been verified by matching the dispersion results with the experimental values published elsewhere View full abstract»

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  • Extraction of channel length and junction voltage in n+/n/n+ or n+/p/n+ polysilicon resistors

    Page(s): 1968 - 1970
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    A method for extraction of channel length and junction voltage of poly-Si resistors is presented. Direct extraction of channel length can be performed for n+/n/n+ resistors operating in the nonlinear I-V regime. However, poly-Si resistors may have channel doping opposite to that of the source/drain doping. For this case, a method is presented for extraction of the current-dependent voltage drop across the drain n+/p junction. Importantly, this junction voltage drop can be an appreciable fraction of the drain-to-source bias and thus is important for correct analysis of n+/p/n+ resistors View full abstract»

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  • The process window of a-Si/Ti bilayer metallization for an oxidation-resistant and self-aligned TiSi2 process

    Page(s): 1835 - 1843
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    The dependences of both oxidation-resistant and self-aligned silicidation properties on the thicknesses of top amorphous-Si (a-Si) and Ti metal in an a-Si/Ti bilayer process are presented. It is shown that a thin silicide layer formed during the reaction between a-Si and Ti films becomes a stable oxidation and nitridation barrier for oxygen- and nitrogen-related impurities. Moreover, the formation sequence of the silicide phase depends not only on the annealing temperature but also on the thickness of the Ti film. In addition, the preferential orientation of the silicide phase after annealing at high temperature also shows a strong dependence on the thickness of Ti film, which is attributed to the difference of the grain size in the polycrystalline silicide film. The allowed process window for the a-Si thickness can be determined experimentally and a reproducible and homogeneous self-aligned TiSi2 film can be easily obtained by using the a-Si/Ti bilayer process in salicide applications despite high-level contaminations of oxygen impurities in both the as-deposited Ti film and the annealing ambient View full abstract»

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  • Limitations of the back-to-back barrier-intrinsic-n+ (BIN) diode frequency tripler

    Page(s): 1805 - 1810
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    Problems of the back-to-back GaAs barrier-intrinsic-n+ (BIN) diode frequency tripler concept along with the associated device physics are presented. The back-to-back GaAs BIN diode structure was originally proposed to have an intrinsic cutoff frequency close to 1 THz and to be a highly efficient millimeter-wave frequency tripler. Frequency limitations will be discussed to explain the failure of the back-to-back GaAs BIN diode as a millimeter-wavelength device. Optimization is also carried out to explore the possibility of improving the high-frequency performance by modifying the BIN diode structure View full abstract»

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  • Physical characterization of hot-electron-induced MOSFET degradation through an improved approach to the charge-pumping technique

    Page(s): 1895 - 1901
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    The physical mechanisms which are involved in the hot-carrier-induced degradation of CMOS transistor are analyzed by means of an improved approach to the charge-pumping measurement technique. The proposed experimental procedure allows the simultaneous characterization of both interface-states generation and carrier trapping in the gate insulator. The analysis is extended to both static and dynamic degradation processes, whose differences and similarities are discussed View full abstract»

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  • Impact ionization and light emission in AlGaAs/GaAs HEMT's

    Page(s): 1849 - 1857
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    Impact ionization and light emission phenomena have been studied in AlGaAs/GaAs HEMTs biased at high drain voltages by measuring the gate excess current due to holes generated by impact ionization and by analyzing the energy distribution of the light emitted from devices in the 1.1-3.1 eV energy range. The emitted spectra in this energy range can be divided into three energy regions: (i) around 1.4 eV light emission is dominated by band-to-band recombination between cold electrons and holes in GaAs; (ii) in the energy range from 1.5 to 2.6 eV energy distribution of the emitted photons is approximately Maxwellian; and (iii) beyond 2.6 eV the spectra are markedly distorted due to light absorption in the n+ GaAs cap layer. The integrated intensity of photons with energies larger than 1.7 eV is proportional to the product of the drain and gate currents. This suggests recombination of channel electrons with holes generated by impact ionization as the dominant emission mechanism of visible light View full abstract»

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  • Schottky contacts on n-In0.53Ga0.47As with enhanced barriers by counter-doped interfacial layers

    Page(s): 1970 - 1972
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    The authors report the preparation and properties of Schottky contacts on n-InGaAs structures. The barrier height is enhanced by counter-doped p+-InGaAs layers (zinc-doped, NA =8×1018 cm-3, d=30 and 60 nm), situated between an n-InGaAs active layer and a barrier metal. Schottky diodes exhibit low reverse current densities, JR =5×10-6 A/cm2, the ideality factor is near unity, n=1.12, and effective barrier heights are 0.66-0.68 eV View full abstract»

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  • Simulation of ultra-small GaAs MESFET's using quantum moment equations. II. Velocity overshoot

    Page(s): 1793 - 1796
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    For Pt.I see ibid., vol.39, p.473-8 (March 1992). The physical physical effects inherent in the operation of ultra-small devices are based on the fact that the critical length (e.g. the gate length or the depletion length) becomes so small that it approaches the coherence length of the electrons that provide the operation which suggests that such small devices must be treated as quantum-mechanical objects. In a previous paper, the authors described the accurate simulation of ultra-small devices, which requires quantum effects such as tunneling and quantum repulsion (complementary to barrier penetration) to be included. This numerical model is based upon a full quantum description based upon moments of the Wigner distribution function. Numerical simulation of ultrasmall MESFETs has been carried out using this model. Here, the authors emphasize the velocity overshoot and other hot-carrier effects and the change of these due to the quantum effects View full abstract»

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  • The minority carrier injection controlled field-effect transistor (MICFET): a new MOS-gated power transistor structure

    Page(s): 1954 - 1960
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    A description is given of a power device structure, the minority carrier injection controlled field-effect transistor (MICFET), in which a floating p region coupled to the drain via a MOSFET is used to inject minority carriers (holes) into the JFET and upper drift region of the DMOSFET to modulate the conductivity of the device during the on-state. The results of device modeling, two-dimensional numerical simulation, and measurements performed on 500-V devices indicate a 30% improvement in on-state current density over the DMOSFET with comparable turn-off times View full abstract»

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  • Modeling of the low-frequency base resistance of single base contact bipolar transistors

    Page(s): 1966 - 1968
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    The current and geometry dependence of the base resistance of single base contact (SBC) bipolar transistors is accurately modeled by extending the simple analytical formulas given by T. Ohzone et al. (1985). The results show that SBC transistors only seem to be useful if the ratio of emitter width b to emitter length l is larger than about 1/5. Of course, this limit depends on technology and circuit application View full abstract»

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  • Heterojunction IMPATT diodes

    Page(s): 1829 - 1834
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    Heterojunction IMPATT diodes, which incorporate an abrupt GaAs/Al 0.3Ga0.7As p/N heterojunction in place of the standard p/n junction, have shown a number of significant properties that represent a considerable technological advance. Ku-band experimental devices exhibit up to 2.0 dB higher power, superior DC characteristics, and 3-6 dB less phase noise content. These and other properties are examined in detail, and a first-order theory of operation is proposed View full abstract»

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  • Developer selection for T-shaped gate FET's using PMMA/P[MMA-co-MAA]/PMMA

    Page(s): 1844 - 1848
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    A T-shaped gate fabrication process has been developed based on a triple-layer resist system with gate cross section control by resist developer formulation. The new procedure allows a conventional e-beam exposure and single develop step to accomplish what requires position dependent e-beam doses or multiple exposures and multiple develop steps in other processes. General considerations in developer selection are discussed. For the process conditions used in this study, gate lengths from 80 to 280 nm were obtained from doses from 250 to 350 μC/cm2 with 20-keV electrons. Initial results on RF performance for a 1.2-mm periphery power FET are given View full abstract»

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  • A simplified and efficient numerical model for charge injection in acoustic charge transport devices

    Page(s): 1811 - 1820
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    A numerically efficient model for simulating electrical charge injection in acoustic charge transport (ACT) devices is developed. This model simplifies an existing charge injection model and is derived using the coupled set of semiconductor device equations. The present model increases the computational efficiency of decoupling and reducing the number of mathematical equations forming the charge injection model. A brief overview of the original model is presented. The assumptions leading to the decoupling and reduction of the device equations are described, as are differences between the two models. Results computed by the simplified model are shown and compared to the results from the original charge injection model and experimental measurement. The present model is able to examine 45 SAW wave positions and 163 contact voltages in 8 h on a 25 MHz PC in comparison to the previous model which simulated 59 wave positions and 164 contact voltages on an Hewlett-Packard 9000 series 500 minicomputer in 37 h. A substantial reduction in computation time is achieved View full abstract»

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  • The field-assisted turn-off thyristor: a regenerative device with voltage-controlled turn-off

    Page(s): 1946 - 1953
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    A solid-state switching element, the field-assisted turn-off (FATO) thyristor, has been developed. This is a regenerative device, which implies that it is capable of carrying very large current densities, with a very small forward voltage drop when it is in its on-state. Most regenerative devices cannot be turned off with a control signal; however, the structure of the FATO thyristor allows it to be switched off by applying a voltage to a high impedance, insulated-gate terminal. This device can also be fabricated with an insulated-gate turn-on structure, so that it is fully switchable using only low-current control signals. The design, fabrication, and characterization of the FATO thyristor are described View full abstract»

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  • Reduction of oxide charge and interface-trap density in MOS capacitors with ITO gates

    Page(s): 1889 - 1894
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    The electrical properties of MOS capacitors with an indium tin oxide (ITO) gate are studied in terms of the number density of the fixed oxide charge and of the interface traps Nf and N it, respectively. Both depend on the deposition conditions of ITO and the subsequent annealing procedures. The fixed oxide charge and the interface-trap density are minimized by depositing at a substrate temperature of 240°C at low power conditions and in an oxygen-rich ambient. Under these conditions, as-deposited ITO films are electrically conductive. The most effective annealing procedure consists of a two-step anneal: a 45-s rapid thermal anneal at 950°C in N2, followed by a 30 min anneal in N2/20% H2 at 450°C. Typical values obtained for Nit and Nf are 4.2×1010 cm-2 and 2.8×1010 cm-2, respectively. These values are further reduced to 1.9×1010 cm-2 and ≲5×109 cm-2, respectively, by depositing approximately 25 nm polycrystalline silicon on the gate insulation prior to the deposition of ITO View full abstract»

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  • A new self-alignment technology using bridged base electrode for small-scaled AlGaAs/GaAs HBT's

    Page(s): 1786 - 1792
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    The fabrication and characterization of a new self-aligned HBT utilizing bridged base-electrode technology (BBT) are presented. This new technology simplifies the fabrication process and relaxes the limitations in device size scaling, thus decreasing the emitter size to 1 μm×1 μm. In spite of a large junction periphery area ratio, a good current gain of more than 10 is obtained in an HBT with an emitter size of 1 μm×1 μm. A series of fabricated HBTs shows excellent high-speed performance. The highest values of fT =90 GHz and fmax=63 GHz are obtained in an HBT with an emitter size of 1 μm×5 μm. The realization of HBTs with small emitters and excellent high-frequency characteristics demonstrates the effectiveness of this new technology View full abstract»

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  • MOSFET drain engineering analysis for deep-submicrometer dimensions: a new structural approach

    Page(s): 1922 - 1927
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    A new MOS transistor structural approach (hot-carrier-induced MOSFET) capable of substantially suppressing adverse hot-carrier effects, while maintaining the other desired performance and manufacturability characteristics of deep-submicrometer MOSFETs (L gate⩽0.35 μm) is described. This structure is unique in having a lower doped N- region located behind (or above) a very shallow, steeply profiled source/drain junction. In contrast, LDD types of MOSFETs have an N- region with a more graded doping profile immediately adjacent to the channel region. The simulated characteristics of the HCS MOSFET structure indicate approximately one order of magnitude less substrate current in comparison to an LDD type of MOSFET whose structure and doping parameters are optimized for combined performance, reliability, and manufacturability. In terms of combined performance, reliability, and manufacturability, the HCS MOSFET should permit MOSFET devices to be more successfully scaled at deep-submicrometer dimensions View full abstract»

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  • Series resistance of silicided ohmic contacts for nanoelectronics

    Page(s): 1882 - 1888
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    The electrical behavior of shallow silicide-to-silicon ohmic contacts has been evaluated for lateral dimensions to 50 nm. Trench-isolated series resistance test structures were fabricated using TiSi2 self-aligned contact technology. Resistance measurements have been performed as a function of contact size in the temperature range from 100 to 300 K and analyzed using multidimensional resistor ladder network models. Well-behaved small-volume ohmic contacts have been achieved. Large-area contact characteristics can be maintained to the smallest sizes. Multidimensional current flow has little effect on the measured resistances. Small lateral dimensional variations are responsible for the higher than predicted series resistance for the smallest sizes. The implications on nanoelectronic devices and circuits are quantified View full abstract»

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  • Optimal second-order small-signal model for long- and short-channel three-terminal MOSFET/MODFET wave equation

    Page(s): 1909 - 1915
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    An optimal second-order small-signal model is developed for the long-channel three-terminal MOSFET/MODFET wave equation. The resulting Y parameters admit the correct fourth-order frequency power series expansion and exhibit a graceful degradation at high frequencies compared to a previously reported second-order model. This model can be integrated in the velocity-saturated MOSFET/MODFET equivalent circuit and is demonstrated to greatly improve the frequency range of validity of this short-channel model. The excellent results obtained demonstrate the validity of both the equivalent-circuit synthesis procedure and the correctness of the equivalent circuit proposed View full abstract»

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IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

 

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John D. Cressler
School of Electrical and Computer Engineering
Georgia Institute of Technology