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Design & Test of Computers, IEEE

Issue 2 • Date June 1992

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Displaying Results 1 - 7 of 7
  • VHDL: toward a unified view of design

    Page(s): 8 - 17
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (905 KB)  

    A high-level view of the relevance of and relationships between key events in the development of the very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) is presented. Three phases in the life cycle of the language, the definition, development, and deployment phases, are outlined. The concept of a design information space, a convenient abstraction for categorizing various VHDL efforts and understanding their interrelationships, is introduced. Two representative VHDL examples dealing with performance modeling and testing are discussed. The waveform and vector exchange specification (WAVES) VHDL subset for the exchange of waveform descriptions is described.<> View full abstract»

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  • DSS: a distributed high-level synthesis system

    Page(s): 18 - 32
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1321 KB)  

    DSS, a large-scale ongoing exercise in developing parallel algorithms for high-level synthesis and implementing them in an integrated distributed system to evaluate their individual and collective effectiveness, is discussed. Embedded in a very-high-speed integrated circuit hardware description language (VHDL) centered design environment, DSS consists of a collection of parallel algorithms executing on a multiple input, multiple data (MIMD) multiprocessor machine. The system uses coarse-grained parallelism to explore and evaluate many alternative VLSI designs efficiently. DSSs internal organization and its scheduling, register optimization, interconnection formation, and controller generation techniques are described. Results illustrating DSS performance with respect to design quality, and the efficiency of the DSS algorithms in a multiprocessor environment are presented.<> View full abstract»

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  • A VHDL fault diagnosis tool using functional fault models

    Page(s): 33 - 41
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1217 KB)  

    The development and implementation of an algorithm that forms the basis of a very-high-speed integrated circuit hardware description language (VHDL) fault diagnosis tool (VFDT) are discussed. Given a VHDL description, a compiler creates an internal representation suitable for simulation and fault diagnosis. VFDT diagnoses faults in this representation hierarchically using the stuck-at fault model at the first level and the arbitrary-failure model at the second level. It reasons from first principles by means of constraint suspension. Examples of fault diagnosis using the VFDT are described.<> View full abstract»

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  • Formal verification of VHDL descriptions in the Prevail environment

    Page(s): 42 - 56
    Save to Project icon | Request Permissions | Click to expandQuick Abstract | PDF file iconPDF (1465 KB)  

    Prevail, a formal verification environment for proving the equivalence of two very-high-speed integrated circuit hardware description language (VHDL) design architectures, is described. For simple bit-level combinational descriptions, the environment calls upon a tautology checker. For parameterized repetitive structures and for more abstract sequential designs, the program translates descriptions into recursive functions according to predefined templates and generates a theorem acceptable to the Bover-Moore theorem prover. The specification, implementation, and functional representation of a sequential example are presented.<> View full abstract»

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  • Specification, planning, and synthesis in a VHDL design environment

    Page(s): 58 - 68
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    Silicon 1076, a very-high-speed integrated circuit hardware description language (VHDL) design environment developed for specifying, simulating, and synthesizing digital hardware, is described. The environment integrates software tools for architectural-level design space exploration and synthesis and RTL synthesis. Silicon 1076 supports a top-down design methodology, while making use of bottom-up design information such as area and delay of modules and interconnect and routing estimates. The flexible design environment allows the user to describe separate parts of the design at different abstraction levels and to perform mixed-level VHDL simulation and synthesis. With the synthesis tools, the user can perform high-level what-if analysis and planning by constraining and exploring portions of the design space.<> View full abstract»

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  • Three decades of HDLs. I. CDL through TI-HDL

    Page(s): 69 - 81
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    Current hardware description languages (HDLs) benefit from the efforts of designers of hardware description languages dating back to the mid 1960s. The developers of six HDLs discuss their motivations and their views of how their work relates to the present very-high-speed integrated circuit HDLs (VHDLs). The languages discussed are Computer Design Languages (CDL). Digital Systems Design Languages (DDL). A Hardware Programming Language (AHPL), Instruction Set Processor Specifications (ISPS), Instruction Set Processor Prime (ISP'), and Texas Instruments Hardware Description Language (TI-HDL).<> View full abstract»

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  • A D&T special report-boundary scan: and end-of-term report-IEEE Std 1149.1 survey results

    Page(s): 82 - 85
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    The level of commercial support for and the extent to which manufacturers are using IEEE Std 1149.1 Standard Test-Access Port and Boundary-Scan Architecture in their products are described. The author's involvement in the IEEE 1149.1 Working Group is discussed View full abstract»

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Aims & Scope

This Periodical ceased production in 2012. The current retitled publication is IEEE Design & Test.

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Editor-in-Chief
Krishnendu Chakrabarty