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# IEEE Transactions on Electron Devices

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Displaying Results 1 - 25 of 36
• ### Modeling submicrometer GaAs MESFETs using PISCES with an apparent gate-length-dependent velocity-field relation

Publication Year: 1992, Page(s):1778 - 1780
Cited by:  Papers (2)
| | PDF (276 KB)

An empirical velocity-field relationship, based on Monte Carlo simulation, is integrated into the PISCES drift-diffusion simulation program in order to analyze short-gate GaAs MESFETs. The current-voltage characteristics are compared with 2D Monte Carlo simulation results on a 0.2 μm gate length and with measured I-V characteristics of a 0.32 μm gate-length GaAs MESFET. The... View full abstract»

• ### Monte Carlo simulation of boron implantation into single-crystal silicon

Publication Year: 1992, Page(s):1614 - 1621
Cited by:  Papers (65)
| | PDF (756 KB)

An improved Monte Carlo simulation model has been developed for boron implantation into single-crystal silicon. This model is based on the Marlowe Monte Carlo code and contains significant improvements for the modeling of ion implantation, including a newly developed local electron concentration-dependent electronic stopping model and a newly developed cumulative damage model. These improvements a... View full abstract»

• ### Effect of traps on the response of a photoexcited GaAs MESFET

Publication Year: 1992, Page(s):1776 - 1778
Cited by:  Papers (1)
| | PDF (264 KB)

Photoinjected carriers were found to cause modulation of the drain-source current of a MESFET biased in the active region. The observed tail in the temporal response is attributed to the modulation of the channel by trapped charges View full abstract»

• ### Cubic paraelectric (nonferroelectric) perovskite PLT thin films with high permittivity for ULSI DRAMs and decoupling capacitors

Publication Year: 1992, Page(s):1607 - 1613
Cited by:  Papers (58)  |  Patents (2)
| | PDF (764 KB)

Polycrystalline paraelectric perovskite thin films in the Pb-La-Ti-O or PLT (28 mol.% La) system have been studied. Thin (0.5-μm) films were integrated onto 3-in Pt/Ti/SiO2/(100) Si wafers by the sol-gel processing technique. Low-field dielectric measurements yielded dielectric permittivity and loss tangent of 1400 and 0.015, respectively, while high-field Sawyer-Tower measurements (... View full abstract»

• ### Hot-carrier stress damage in the gate off' state in n-channel transistors

Publication Year: 1992, Page(s):1774 - 1776
Cited by:  Papers (10)
| | PDF (264 KB)

Hot-carrier damage in the of' state (Vg⩽ Vt while Vd is high, V g(off)) in silicon n-MOS transistors is examined. This condition commonly occurs due to capacitively coupled noise at the input of a CMOS inverter. It is shown that damage can occur under these conditions in the form of oxide trapped charge. Contrary ... View full abstract»

• ### A nonrecessed-base, self-aligned bipolar structure with selectively deposited polysilicon emitter

Publication Year: 1992, Page(s):1711 - 1716
Cited by:  Papers (3)
| | PDF (660 KB)

A self-aligned bipolar structure, which features a nonrecessed base and a selectively deposited polysilicon emitter, is proposed. The in situ surface cleaning process prior to the selective-polysilicon deposition minimizes the residual native oxide in the emitter window. Both high-quality selective-polysilicon film and well-behaved submicrometer bipolar device characteristics have been obtained fo... View full abstract»

• ### Simulation of elevated temperature aluminum metallization using SIMBAD

Publication Year: 1992, Page(s):1599 - 1606
Cited by:  Papers (35)  |  Patents (1)
| | PDF (716 KB)

A ballistic deposition model, SIMBAD, has been extended to simulate physical vapor deposition onto substrates at elevated temperatures. The model has been expanded to account for the effect of film curvature on surface diffusion. The effects on via coverage and filling have been simulated for aluminum films, and complete planarization of a 1:1 aspect ratio via is predicted for a temperature of 550... View full abstract»

• ### Investigation of SOI-like I-V characteristics for a 64-Mb DRAM SCC MOSFET with a buried drain

Publication Year: 1992, Page(s):1652 - 1660
Cited by:  Papers (1)  |  Patents (2)
| | PDF (832 KB)

The MOSFET structure of a surrounding-high-capacitance cell (SCC) trench cell with a buried drain scaled down for 64-Mb DRAM applications has been studied using the device simulator MINIMOS. For this cell design, the depletion zones of the buried drain can pinch off the substrate at a sufficiently high drain bias. The resulting floating substrate causes sharply increased avalanche carrier generati... View full abstract»

• ### Improved drift in two-phase, long-channel, shallow buried-channel CCDs with longitudinally nonuniform storage-gate implants

Publication Year: 1992, Page(s):1772 - 1774
Cited by:  Papers (4)  |  Patents (1)
| | PDF (316 KB)

Two-phase buried-channel charge-coupled devices (CCDs) with a gradient in the storage wells, generated by a nonuniform channel doping parallel to the surface, were studied at room temperature and at 77 K. The built-in drift fields improve the charge transfer efficiency by more than an order of magnitude, consistently with two-dimensional simulations View full abstract»

• ### Scaling the Si MOSFET: from bulk to SOI to bulk

Publication Year: 1992, Page(s):1704 - 1710
Cited by:  Papers (435)  |  Patents (136)
| | PDF (576 KB)

Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vert... View full abstract»

• ### Efficient light scattering modeling for alignment, metrology, and resist exposure in photolithography

Publication Year: 1992, Page(s):1588 - 1598
Cited by:  Papers (15)
| | PDF (840 KB)

In previous work, a two-dimensional waveguide model has been developed and examined extensively so that rigorous light scattering calculations for photolithography-related processes, such as stepper alignment, linewidth and overlay measurements, and resist bleaching, can be performed. The computation, however, is expensive if the wafer topography involved is complicated or if resist bleaching prob... View full abstract»

• ### A quantitative physical model for the band-to-band tunneling-induced substrate hot electron injection in MOS devices

Publication Year: 1992, Page(s):1646 - 1651
Cited by:  Papers (11)  |  Patents (11)
| | PDF (508 KB)

A quantitative physical model for band-to-band tunneling-induced substrate hot electron (BBISHE) injection in heavily doped n-channel MOSFETs is presented. In BBISHE injection, the injected substrate hot electrons across the gate oxide are generated by impact ionization by the energetic holes which are left behind by the tunneling electrons and become energetic when traveling across the surface hi... View full abstract»

• ### Simple equations for the electrostatic potential in buried-channel MOS devices

Publication Year: 1992, Page(s):1770 - 1772
Cited by:  Papers (3)
| | PDF (256 KB)

Simple equations are presented for the potential in a buried-channel MOS device as a function of channel charge. If either the oxide thickness or the channel charge is reduced to zero, these equations simplify to the equations obtained by others. The predictions of these equations are compared to numerical solutions, and good agreement is found View full abstract»

• ### Quantum-mechanical modeling of accumulation layers in MOS structure

Publication Year: 1992, Page(s):1732 - 1739
Cited by:  Papers (75)  |  Patents (1)
| | PDF (684 KB)

An original method is used for the quantum-mechanical modeling of n-type silicon accumulation layers. Unlike previous methods, which were only valid near 4.2 K, the approach is valid up to room temperature and beyond. The self-consistent results obtained are compared with those of the standard classical model for the accumulation layer, and the differences between them are found to be relevant for... View full abstract»

• ### Two-dimensional analysis of the breakdown mechanism in the etched-groove silicon permeable base transistor

Publication Year: 1992, Page(s):1545 - 1550
Cited by:  Papers (3)
| | PDF (520 KB)

A two-dimensional, two-carrier simulation of a uniformly doped etched-groove permeable-base transistor which includes models for impact ionization and for Auger and Shockley-Read-Hall recombination is reported. It was found that for high current densities the breakdown voltage was reduced by channel avalanche. This mechanism was associated with a strong accumulation of electrons and holes in the s... View full abstract»

• ### Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model

Publication Year: 1992, Page(s):1694 - 1703
Cited by:  Papers (65)  |  Patents (5)
| | PDF (852 KB)

A systematic study of gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described. Design curves quantifying the GIDL dependence on gate oxide thickness, phosphorus dose, and spacer length are presented. In addition, a new, quasi-2-D analytical model is developed for the electric field in the gate-to-drain ... View full abstract»

• ### A new decoupled algorithm for nonstationary, transient simulations of GaAs MESFETs

Publication Year: 1992, Page(s):1578 - 1587
Cited by:  Papers (7)
| | PDF (716 KB)

Simulation of devices for which nonlocal, hot carrier transport cannot be ignored requires solution of the Poisson equation and at least the first three moments of the Boltzmann transport equation or the use of Monte Carlo techniques. These equations form nonlinear, coupled, time-dependent partial differential equations. In conventional decoupled solvers, decoupling of the equations puts a limit o... View full abstract»

• ### A model for the trap-assisted tunneling mechanism in diffused n-p and implanted n+-p HgCdTe photodiodes

Publication Year: 1992, Page(s):1638 - 1645
Cited by:  Papers (40)
| | PDF (652 KB)

A theoretical model for the trap-assisted tunneling process in diffused n-on-p and implanted n+-on-p HgCdTe photodiodes is presented. The model describes the connection between the leakage current associated with the traps and the trap characteristics: concentration, energy level, and capture cross sections. It was observed that the above two types of diodes differ in the voltage depend... View full abstract»

• ### Enhanced electron trapping near channel edges in NMOS transistors

Publication Year: 1992, Page(s):1680 - 1686
Cited by:  Papers (7)
| | PDF (620 KB)

Charge trapping in the gate oxide of NMOS transistors due to constant-voltage Fowler-Nordheim injection was investigated. Results from several different measurement methods consistently indicated strongly enhanced electron trapping in the gate oxide near the channel edges and in the gate oxide overlaps above drain and source, although net positive charge was observed in the bulk of the channel. Th... View full abstract»

• ### A new analytical model for gated turn-off of thyristors

Publication Year: 1992, Page(s):1752 - 1757
Cited by:  Papers (5)
| | PDF (484 KB)

A two-dimensional analytical model is developed to explain the storage phase of the turn-off mechanism in a gate turn-off thyristor. An expression is obtained from first principles for the position of the `on' region plasma edge as a function of time, assuming a negative ramp for the gate current. The model contains no fitting parameters and addresses realistic issues such as high-injection effect... View full abstract»

• ### Numerical analysis of the photoeffects in GaAs MESFET's

Publication Year: 1992, Page(s):1564 - 1570
Cited by:  Papers (10)
| | PDF (516 KB)

The photoeffects on the I-V characteristics of GaAs MESFETs have been studied by a two-dimensional numerical method. It is theoretically verified that the photovoltaic effect occurring at the channel/substrate interface is responsible for the substantial increase of the drain current. The reverse gate current due to illumination is caused by sweep-out by the high electrical field... View full abstract»

• ### Breakdown voltage of field plate and field-limiting ring techniques: numerical comparison

Publication Year: 1992, Page(s):1768 - 1770
Cited by:  Papers (8)  |  Patents (1)
| | PDF (260 KB)

Using the recently developed two-dimensional simulator STAAB, the breakdown voltage of the field plate and field-limiting ring junction termination techniques is numerically compared for various values of junction depth, lateral width, and oxide fixed charge. The computed results demonstrate the superiority of the field plate technique over the field-limiting ring technique for planar shallow-junc... View full abstract»

• ### Space-charge effects in ballistic injection across heterojunctions [FETs]

Publication Year: 1992, Page(s):1780 - 1782
| | PDF (264 KB)

Conditions under which ballistic injection across heterojunctions is suppressed in unipolar FET devices have been examined using two-dimensional Monte Carlo simulation. Gate-induced lateral space charges influence via macroscopic current continuity the dipole layer at the heterojunction. A retarding dipole layer is shown to result in ballistic electron fractions and transit times comparable to tho... View full abstract»

• ### Analysis of the small-signal voltage decay technique in the characterization of Si concentrator solar cells

Publication Year: 1992, Page(s):1622 - 1632
Cited by:  Papers (3)
| | PDF (920 KB)

Detailed analyses of the small-signal voltage decay (SSVD) method of lifetime measurement have been performed. The main difficulty in voltage decay techniques is that the boundary conditions at the junction are coupled. A solution to the time-dependent diffusion equations has been obtained using the quasi-static emitter (QSE) approximation. Assuming a power-law emitter doping profile, a solution t... View full abstract»

• ### Polysilicon emitters for bipolar transistors: a review and re-evaluation of theory and experiment

Publication Year: 1992, Page(s):1717 - 1731
Cited by:  Papers (54)  |  Patents (73)
| | PDF (1396 KB)

A critical review is presented of the theories proposed in the literature to explain the current gain enhancement of polysilicon emitter bipolar transistors. From these theories a simplified analytical formulation is chosen which models the blocking properties of the interface, including tunneling through the interfacial oxide, reduced grain boundary mobility at the polysilicon/silicon interface, ... View full abstract»

## Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.

Full Aims & Scope

## Meet Our Editors

Editor-in-Chief

Giovanni Ghione
Politecnico di Torino,
10129 Torino, Italy